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Searched refs:uvd (Results 1 – 21 of 21) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_uvd.c139 INIT_DELAYED_WORK(&adev->uvd.idle_work, amdgpu_uvd_idle_work_handler); in amdgpu_uvd_sw_init()
196 r = request_firmware(&adev->uvd.fw, fw_name, adev->dev); in amdgpu_uvd_sw_init()
203 r = amdgpu_ucode_validate(adev->uvd.fw); in amdgpu_uvd_sw_init()
207 release_firmware(adev->uvd.fw); in amdgpu_uvd_sw_init()
208 adev->uvd.fw = NULL; in amdgpu_uvd_sw_init()
213 adev->uvd.max_handles = AMDGPU_DEFAULT_UVD_HANDLES; in amdgpu_uvd_sw_init()
215 hdr = (const struct common_firmware_header *)adev->uvd.fw->data; in amdgpu_uvd_sw_init()
234 adev->uvd.max_handles = AMDGPU_MAX_UVD_HANDLES; in amdgpu_uvd_sw_init()
236 adev->uvd.fw_version = ((version_major << 24) | (version_minor << 16) | in amdgpu_uvd_sw_init()
241 (adev->uvd.fw_version < FW_1_66_16)) in amdgpu_uvd_sw_init()
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H A Damdgpu_uvd_v7_0.c96 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_rptr()
130 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_get_wptr()
168 if (ring == &adev->uvd.inst[ring->me].ring_enc[0]) in uvd_v7_0_enc_ring_set_wptr()
384 adev->uvd.num_uvd_inst = UVD7_MAX_HW_INSTANCES_VEGA20; in uvd_v7_0_early_init()
385 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in uvd_v7_0_early_init()
388 adev->uvd.harvest_config |= 1 << i; in uvd_v7_0_early_init()
391 if (adev->uvd.harvest_config == (AMDGPU_UVD_HARVEST_UVD0 | in uvd_v7_0_early_init()
396 adev->uvd.num_uvd_inst = 1; in uvd_v7_0_early_init()
400 adev->uvd.num_enc_rings = 1; in uvd_v7_0_early_init()
402 adev->uvd.num_enc_rings = 2; in uvd_v7_0_early_init()
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H A Damdgpu_uvd_v6_0.c72 (!adev->uvd.fw_version || adev->uvd.fw_version >= FW_1_130_16)); in uvd_v6_0_enc_support()
100 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_get_rptr()
130 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_get_wptr()
161 if (ring == &adev->uvd.inst->ring_enc[0]) in uvd_v6_0_enc_ring_set_wptr()
370 adev->uvd.num_uvd_inst = 1; in uvd_v6_0_early_init()
379 adev->uvd.num_enc_rings = 2; in uvd_v6_0_early_init()
395 …id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); in uvd_v6_0_sw_init()
401 for (i = 0; i < adev->uvd.num_enc_rings; ++i) { in uvd_v6_0_sw_init()
402 …(adev, AMDGPU_IRQ_CLIENTID_LEGACY, i + VISLANDS30_IV_SRCID_UVD_ENC_GEN_PURP, &adev->uvd.inst->irq); in uvd_v6_0_sw_init()
413 for (i = 0; i < adev->uvd.num_enc_rings; ++i) in uvd_v6_0_sw_init()
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H A Damdgpu_uvd_v4_2.c101 adev->uvd.num_uvd_inst = 1; in uvd_v4_2_early_init()
116 r = amdgpu_irq_add_id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, 124, &adev->uvd.inst->irq); in uvd_v4_2_sw_init()
124 ring = &adev->uvd.inst->ring; in uvd_v4_2_sw_init()
126 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); in uvd_v4_2_sw_init()
163 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_hw_init()
218 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_hw_fini()
261 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v4_2_start()
552 addr = (adev->uvd.inst->gpu_addr + AMDGPU_UVD_FIRMWARE_OFFSET) >> 3; in uvd_v4_2_mc_resume()
564 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles)) >> 3; in uvd_v4_2_mc_resume()
569 addr = (adev->uvd.inst->gpu_addr >> 28) & 0xF; in uvd_v4_2_mc_resume()
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H A Damdgpu_uvd_v5_0.c99 adev->uvd.num_uvd_inst = 1; in uvd_v5_0_early_init()
114 …id(adev, AMDGPU_IRQ_CLIENTID_LEGACY, VISLANDS30_IV_SRCID_UVD_SYSTEM_MESSAGE, &adev->uvd.inst->irq); in uvd_v5_0_sw_init()
122 ring = &adev->uvd.inst->ring; in uvd_v5_0_sw_init()
124 r = amdgpu_ring_init(adev, ring, 512, &adev->uvd.inst->irq, 0); in uvd_v5_0_sw_init()
159 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_init()
216 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_hw_fini()
265 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
267 upper_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v5_0_mc_resume()
281 (AMDGPU_UVD_SESSION_SIZE * adev->uvd.max_handles); in uvd_v5_0_mc_resume()
299 struct amdgpu_ring *ring = &adev->uvd.inst->ring; in uvd_v5_0_start()
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H A Damdgpu_kms.c226 fw_info->ver = adev->uvd.fw_version; in amdgpu_firmware_info()
358 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
359 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
362 if (adev->uvd.inst[i].ring.sched.ready) in amdgpu_hw_ip_info()
378 for (i = 0; i < adev->uvd.num_uvd_inst; i++) { in amdgpu_hw_ip_info()
379 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
382 for (j = 0; j < adev->uvd.num_enc_rings; j++) in amdgpu_hw_ip_info()
383 if (adev->uvd.inst[i].ring_enc[j].sched.ready) in amdgpu_hw_ip_info()
392 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
404 if (adev->uvd.harvest_config & (1 << i)) in amdgpu_hw_ip_info()
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H A Damdgpu_fence.c413 index = ALIGN(adev->uvd.fw->size, 8); in amdgpu_fence_driver_start_ring()
414 ring->fence_drv.cpu_addr = adev->uvd.inst[ring->me].cpu_addr + index; in amdgpu_fence_driver_start_ring()
415 ring->fence_drv.gpu_addr = adev->uvd.inst[ring->me].gpu_addr + index; in amdgpu_fence_driver_start_ring()
H A Damdgpu_uvd.h39 …(AMDGPU_GPU_PAGE_ALIGN(le32_to_cpu(((const struct common_firmware_header *)(adev)->uvd.fw->data)->…
H A Damdgpu_ctx.c102 sched = &adev->uvd.inst[0].ring.sched; in amdgpu_ctx_init_entity()
112 sched = &adev->uvd.inst[0].ring_enc[0].sched; in amdgpu_ctx_init_entity()
H A Damdgpu_ucode.c402 FW_VERSION_ATTR(uvd_fw_version, 0444, uvd.fw_version);
H A Damdgpu.h903 struct amdgpu_uvd uvd; member
H A Damdgpu_pm.c3188 adev->uvd.decode_image_width >= WIDTH_4K) { in amdgpu_dpm_enable_uvd()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_uvd.c79 INIT_DELAYED_WORK(&rdev->uvd.idle_work, radeon_uvd_idle_work_handler); in radeon_uvd_init()
144 rdev->uvd.fw_header_present = false; in radeon_uvd_init()
145 rdev->uvd.max_handles = RADEON_DEFAULT_UVD_HANDLES; in radeon_uvd_init()
160 rdev->uvd.fw_header_present = true; in radeon_uvd_init()
173 rdev->uvd.max_handles = RADEON_MAX_UVD_HANDLES; in radeon_uvd_init()
193 RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles; in radeon_uvd_init()
196 NULL, &rdev->uvd.vcpu_bo); in radeon_uvd_init()
202 r = radeon_bo_reserve(rdev->uvd.vcpu_bo, false); in radeon_uvd_init()
204 radeon_bo_unref(&rdev->uvd.vcpu_bo); in radeon_uvd_init()
209 r = radeon_bo_pin(rdev->uvd.vcpu_bo, RADEON_GEM_DOMAIN_VRAM, in radeon_uvd_init()
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H A Dradeon_uvd_v4_2.c51 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume()
52 addr = (rdev->uvd.gpu_addr + 0x200) >> 3; in uvd_v4_2_resume()
54 addr = rdev->uvd.gpu_addr >> 3; in uvd_v4_2_resume()
67 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v4_2_resume()
72 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v4_2_resume()
76 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v4_2_resume()
79 if (rdev->uvd.fw_header_present) in uvd_v4_2_resume()
80 WREG32(UVD_GP_SCRATCH4, rdev->uvd.max_handles); in uvd_v4_2_resume()
H A Dradeon_uvd_v2_2.c118 addr = rdev->uvd.gpu_addr >> 3; in uvd_v2_2_resume()
130 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v2_2_resume()
135 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v2_2_resume()
139 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v2_2_resume()
H A Dradeon_uvd_v1_0.c126 addr = (rdev->uvd.gpu_addr >> 3) + 16; in uvd_v1_0_resume()
138 (RADEON_UVD_SESSION_SIZE * rdev->uvd.max_handles)) >> 3; in uvd_v1_0_resume()
143 addr = (rdev->uvd.gpu_addr >> 28) & 0xF; in uvd_v1_0_resume()
147 addr = (rdev->uvd.gpu_addr >> 32) & 0xFF; in uvd_v1_0_resume()
150 WREG32(UVD_FW_START, *((uint32_t*)rdev->uvd.cpu_addr)); in uvd_v1_0_resume()
H A Dradeon_drv.c312 MODULE_PARM_DESC(uvd, "uvd enable/disable uvd support (1 = enable, 0 = disable)");
313 module_param_named(uvd, radeon_uvd, int, 0444);
H A Dradeon_fence.c902 rdev->fence_drv[ring].cpu_addr = (uint32_t *)((uint8_t *)rdev->uvd.cpu_addr + index); in radeon_fence_driver_start_ring()
903 rdev->fence_drv[ring].gpu_addr = rdev->uvd.gpu_addr + index; in radeon_fence_driver_start_ring()
H A Dradeon.h2447 struct radeon_uvd uvd; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/
H A Dsmu10_hwmgr.h114 uint32_t uvd : 1; member
H A Dsmu8_hwmgr.h137 uint32_t uvd : 1; member