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Searched refs:upper_32_bits (Results 1 – 25 of 177) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c63 packet->sq_shader_tba_hi = upper_32_bits(qpd->tba_addr >> 8) in pm_map_process_v9()
67 packet->sq_shader_tma_hi = upper_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
71 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_v9()
76 upper_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
114 packet->ib_base_hi = upper_32_bits(ib); in pm_runlist_v9()
139 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_v9()
142 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_v9()
203 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_v9()
209 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9()
308 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_v9()
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H A Dkfd_packet_manager_vi.c74 packet->gds_addr_hi = upper_32_bits(qpd->gds_context_area); in pm_map_process_vi()
113 packet->bitfields3.ib_base_hi = upper_32_bits(ib); in pm_runlist_vi()
138 packet->gws_mask_hi = upper_32_bits(res->gws_mask); in pm_set_resources_vi()
141 packet->queue_mask_hi = upper_32_bits(res->queue_mask); in pm_set_resources_vi()
193 upper_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
199 upper_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
287 packet->addr_hi = upper_32_bits((uint64_t)fence_address); in pm_query_status_vi()
289 packet->data_hi = upper_32_bits((uint64_t)fence_value); in pm_query_status_vi()
317 packet->address_hi = upper_32_bits(gpu_addr); in pm_release_mem_vi()
H A Dkfd_mqd_manager_vi.c121 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
135 m->compute_tba_hi = upper_32_bits(q->tba_addr >> 8); in init_mqd()
137 m->compute_tma_hi = upper_32_bits(q->tma_addr >> 8); in init_mqd()
148 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
189 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
192 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in __update_mqd()
194 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in __update_mqd()
221 upper_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
362 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
364 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_v10.c117 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
134 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
182 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
185 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
187 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
209 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
339 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
341 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_v9.c152 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
174 upper_32_bits(q->ctx_save_restore_area_address); in init_mqd()
219 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
222 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd()
224 m->cp_hqd_pq_wptr_poll_addr_hi = upper_32_bits((uint64_t)q->write_ptr); in update_mqd()
248 upper_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
382 m->sdmax_rlcx_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
384 m->sdmax_rlcx_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_cik.c121 m->cp_mqd_base_addr_hi = upper_32_bits(addr); in init_mqd()
212 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
214 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in __update_mqd()
253 m->sdma_rlc_rb_base_hi = upper_32_bits(q->queue_address >> 8); in update_mqd_sdma()
255 m->sdma_rlc_rb_rptr_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
335 m->cp_hqd_pq_base_hi = upper_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
337 m->cp_hqd_pq_rptr_report_addr_hi = upper_32_bits((uint64_t)q->read_ptr); in update_mqd_hiq()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_si_dma.c81 amdgpu_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in si_dma_ring_emit_ib()
103 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
110 amdgpu_ring_write(ring, (upper_32_bits(addr) & 0xff)); in si_dma_ring_emit_fence()
111 amdgpu_ring_write(ring, upper_32_bits(seq)); in si_dma_ring_emit_fence()
164 WREG32(DMA_RB_RPTR_ADDR_HI + sdma_offsets[i], upper_32_bits(rptr_addr) & 0xFF); in si_dma_start()
230 amdgpu_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in si_dma_ring_test_ring()
281 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in si_dma_ring_test_ib()
329 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pte()
330 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pte()
352 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in si_dma_vm_write_pte()
[all …]
H A Damdgpu_sdma_v2_4.c270 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v2_4_ring_emit_ib()
321 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
329 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
330 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
462 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v2_4_gfx_resume()
577 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
630 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
684 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v2_4_vm_copy_pte()
686 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_copy_pte()
709 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v2_4_vm_write_pte()
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H A Damdgpu_sdma_v5_0.c245 amdgpu_ring_write(ring, upper_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
341 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
344 adev->wb.wb[ring->wptr_offs + 1] = upper_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
355 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
359 upper_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
406 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v5_0_ring_emit_ib()
409 amdgpu_ring_write(ring, upper_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
462 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
473 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
474 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
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H A Damdgpu_cik_sdma.c240 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr) & 0xffffffff); in cik_sdma_ring_emit_ib()
288 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
296 amdgpu_ring_write(ring, upper_32_bits(addr)); in cik_sdma_ring_emit_fence()
297 amdgpu_ring_write(ring, upper_32_bits(seq)); in cik_sdma_ring_emit_fence()
483 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
641 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
694 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
744 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pte()
746 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_copy_pte()
769 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in cik_sdma_vm_write_pte()
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H A Damdgpu_sdma_v3_0.c444 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v3_0_ring_emit_ib()
495 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
503 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
504 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
701 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v3_0_gfx_resume()
727 upper_32_bits(wptr_gpu_addr)); in sdma_v3_0_gfx_resume()
849 amdgpu_ring_write(ring, upper_32_bits(gpu_addr)); in sdma_v3_0_ring_test_ring()
902 ib.ptr[2] = upper_32_bits(gpu_addr); in sdma_v3_0_ring_test_ib()
955 ib->ptr[ib->length_dw++] = upper_32_bits(src); in sdma_v3_0_vm_copy_pte()
957 ib->ptr[ib->length_dw++] = upper_32_bits(pe); in sdma_v3_0_vm_copy_pte()
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H A Damdgpu_sdma_v4_0.c707 upper_32_bits(ring->wptr << 2)); in sdma_v4_0_ring_set_wptr()
720 upper_32_bits(ring->wptr << 2)); in sdma_v4_0_ring_set_wptr()
724 upper_32_bits(ring->wptr << 2)); in sdma_v4_0_ring_set_wptr()
775 upper_32_bits(wptr)); in sdma_v4_0_page_ring_set_wptr()
814 amdgpu_ring_write(ring, upper_32_bits(ib->gpu_addr)); in sdma_v4_0_ring_emit_ib()
886 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v4_0_ring_emit_fence()
896 amdgpu_ring_write(ring, upper_32_bits(addr)); in sdma_v4_0_ring_emit_fence()
897 amdgpu_ring_write(ring, upper_32_bits(seq)); in sdma_v4_0_ring_emit_fence()
1113 upper_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in sdma_v4_0_gfx_resume()
1149 upper_32_bits(wptr_gpu_addr)); in sdma_v4_0_gfx_resume()
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H A Damdgpu_vcn_v1_0.c314 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
326 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
334 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
384 upper_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
396 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
407 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
920 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v1_0_start_spg_mode()
926 upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
944 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
951 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI2, upper_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
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H A Damdgpu_vcn_v2_0.c326 upper_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
338 upper_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
346 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
384 upper_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
405 upper_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
425 upper_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
856 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_0_start_dpg_mode()
862 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
1016 upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1029 WREG32_SOC15(UVD, 0, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
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H A Damdgpu_uvd_v7_0.c246 ib->ptr[ib->length_dw++] = upper_32_bits(addr); in uvd_v7_0_enc_get_create_msg()
308 ib->ptr[ib->length_dw++] = upper_32_bits(addr); in uvd_v7_0_enc_get_destroy_msg()
681 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
692 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_mc_resume()
699 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
728 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_HI, upper_32_bits(addr)); in uvd_v7_0_mmsch_start()
823 upper_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
835 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_sriov_start()
842 upper_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_sriov_start()
909 …MMSCH_V1_0_INSERT_DIRECT_WT(SOC15_REG_OFFSET(UVD, i, mmUVD_RB_BASE_HI), upper_32_bits(ring->gpu_ad… in uvd_v7_0_sriov_start()
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H A Damdgpu_vcn_v2_5.c411 upper_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
422 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
430 upper_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
467 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
488 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
508 upper_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
869 (upper_32_bits(ring->gpu_addr) >> 2)); in vcn_v2_5_start_dpg_mode()
875 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
1048 upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1060 WREG32_SOC15(UVD, i, mmUVD_RB_BASE_HI, upper_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_si_dma.c88 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_copy_pages()
89 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in si_dma_vm_copy_pages()
127 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_write_pages()
139 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_write_pages()
179 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in si_dma_vm_set_pages()
183 ib->ptr[ib->length_dw++] = upper_32_bits(value); in si_dma_vm_set_pages()
271 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in si_copy_dma()
272 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in si_copy_dma()
H A Dradeon_ni_dma.c140 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in cayman_dma_ring_ib_execute()
151 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in cayman_dma_ring_ib_execute()
228 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFF); in cayman_dma_resume()
336 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_copy_pages()
337 ib->ptr[ib->length_dw++] = upper_32_bits(src) & 0xff; in cayman_dma_vm_copy_pages()
376 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_write_pages()
388 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_write_pages()
428 ib->ptr[ib->length_dw++] = upper_32_bits(pe) & 0xff; in cayman_dma_vm_set_pages()
432 ib->ptr[ib->length_dw++] = upper_32_bits(value); in cayman_dma_vm_set_pages()
H A Dradeon_r600_dma.c149 upper_32_bits(rdev->wb.gpu_addr + R600_WB_DMA_RPTR_OFFSET) & 0xFF); in r600_dma_resume()
260 radeon_ring_write(ring, upper_32_bits(gpu_addr) & 0xff); in r600_dma_ring_test()
300 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in r600_dma_fence_ring_emit()
327 radeon_ring_write(ring, upper_32_bits(addr) & 0xff); in r600_dma_semaphore_ring_emit()
365 ib.ptr[2] = upper_32_bits(gpu_addr) & 0xff; in r600_dma_ib_test()
420 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in r600_dma_ring_ib_execute()
431 radeon_ring_write(ring, (ib->length_dw << 16) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in r600_dma_ring_ib_execute()
483 radeon_ring_write(ring, (((upper_32_bits(dst_offset) & 0xff) << 16) | in r600_copy_dma()
484 (upper_32_bits(src_offset) & 0xff))); in r600_copy_dma()
H A Dradeon_cik_sdma.c151 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr)); in cik_sdma_ring_ib_execute()
161 radeon_ring_write(ring, upper_32_bits(ib->gpu_addr)); in cik_sdma_ring_ib_execute()
214 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_fence_ring_emit()
243 radeon_ring_write(ring, upper_32_bits(addr)); in cik_sdma_semaphore_ring_emit()
406 upper_32_bits(rdev->wb.gpu_addr + wb_offset) & 0xFFFFFFFF); in cik_sdma_gfx_resume()
620 radeon_ring_write(ring, upper_32_bits(src_offset)); in cik_copy_dma()
622 radeon_ring_write(ring, upper_32_bits(dst_offset)); in cik_copy_dma()
676 radeon_ring_write(ring, upper_32_bits(gpu_addr)); in cik_sdma_ring_test()
734 ib.ptr[2] = upper_32_bits(gpu_addr); in cik_sdma_ib_test()
823 ib->ptr[ib->length_dw++] = upper_32_bits(src); in cik_sdma_vm_copy_pages()
[all …]
H A Dradeon_evergreen_dma.c54 radeon_ring_write(ring, (upper_32_bits(addr) & 0xff)); in evergreen_dma_fence_ring_emit()
84 radeon_ring_write(ring, upper_32_bits(ring->next_rptr_gpu_addr) & 0xff); in evergreen_dma_ring_ib_execute()
95 radeon_ring_write(ring, (ib->length_dw << 12) | (upper_32_bits(ib->gpu_addr) & 0xFF)); in evergreen_dma_ring_ib_execute()
148 radeon_ring_write(ring, upper_32_bits(dst_offset) & 0xff); in evergreen_copy_dma()
149 radeon_ring_write(ring, upper_32_bits(src_offset) & 0xff); in evergreen_copy_dma()
H A Dradeon_evergreen_cs.c1853 ib[idx + 1] = (tmp & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
1899 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1934 ib[idx+1] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
1962 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2055 ib[idx+2] = upper_32_bits(reloc->gpu_offset) & 0xff; in evergreen_packet3_check()
2135 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2196 ib[idx+1] = (ib[idx+1] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
2234 ib[idx+3] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2282 ib[idx+2] = upper_32_bits(offset) & 0xff; in evergreen_packet3_check()
2304 ib[idx+2] = (ib[idx+2] & 0xffffff00) | (upper_32_bits(offset) & 0xff); in evergreen_packet3_check()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/
H A Dnouveau_nvkm_subdev_pmu_gm20b.c89 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
92 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
95 hdr.overlay_dma_base1 = upper_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
119 .code_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
120 .data_dma_base1 = upper_32_bits(data), in gm20b_pmu_acr_bld_write()
121 .overlay_dma_base1 = upper_32_bits(code), in gm20b_pmu_acr_bld_write()
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
H A Dnouveau_nvkm_engine_gr_gm20b.c47 hdr.code_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
50 hdr.data_dma_base1 = upper_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
71 .code_dma_base1 = upper_32_bits(code), in gm20b_gr_acr_bld_write()
72 .data_dma_base1 = upper_32_bits(data), in gm20b_gr_acr_bld_write()
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gt/
H A Dintel_lrc_reg.h40 (reg_state__)[CTX_PDP ## n ## _UDW] = upper_32_bits(addr__); \
47 (reg_state__)[CTX_PDP0_UDW] = upper_32_bits(addr__); \

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