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/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DTargetPfmCounters.td24 // The name of the ProcResource on which uops are issued. This is used by
37 // Processors can define how to measure uops by defining a UopsCounter.
39 // Processors can define how to measure issued uops by defining IssueCounters.
H A DTargetItinerary.td111 list<Bypass> bypasses = [], int uops = 1> {
113 int NumMicroOps = uops;
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Dppro.md71 ;; two uops, and simple read-modify instructions also take two uops.
72 ;; Simple instructions of the register-memory form have two to three uops.
73 ;; Simple read-modify-write instructions have four uops. The rules for
77 ;; - an instruction with 1 to 4 uops can be decoded only by decoder 0
82 ;; The goal is to schedule such that we have a few-one-one uops sequence
99 ;; so the maximum number of dispatched uops per cycle is 5. In practicer,
100 ;; 3 uops per cycle is more realistic.
125 ;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
129 ;; For microcoded instructions we don't know how many uops are produced.
131 ;; we _do_ know is that they typically produce four or more uops, so
[all …]
H A Dcore2.md53 ;; - an instruction with 1 to 4 uops can be decoded only by decoder 0
58 ;; The goal is to schedule such that we have a few-one-one uops sequence
92 ;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
96 ;; For microcoded instructions we don't know how many uops are produced.
98 ;; we _do_ know is that they typically produce four or more uops, so
166 ;; Shift and rotate decode as two uops which can go to port 0 or 5.
677 ;; register-memory instructions have three uops, so they have to be
685 ;; read-modify-store instructions produce 4 uops so they have to be
H A Dhaswell.md612 ;; read-modify-store instructions produce 4 uops so they have to be
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Dppro.md71 ;; two uops, and simple read-modify instructions also take two uops.
72 ;; Simple instructions of the register-memory form have two to three uops.
73 ;; Simple read-modify-write instructions have four uops. The rules for
77 ;; - an instruction with 1 to 4 uops can be decoded only by decoder 0
82 ;; The goal is to schedule such that we have a few-one-one uops sequence
99 ;; so the maximum number of dispatched uops per cycle is 5. In practicer,
100 ;; 3 uops per cycle is more realistic.
125 ;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
129 ;; For microcoded instructions we don't know how many uops are produced.
131 ;; we _do_ know is that they typically produce four or more uops, so
[all …]
H A Dcore2.md53 ;; - an instruction with 1 to 4 uops can be decoded only by decoder 0
58 ;; The goal is to schedule such that we have a few-one-one uops sequence
92 ;; reg-reg operation, 1 uop per load on port 2. and 2 uops per store
96 ;; For microcoded instructions we don't know how many uops are produced.
98 ;; we _do_ know is that they typically produce four or more uops, so
166 ;; Shift and rotate decode as two uops which can go to port 0 or 5.
677 ;; register-memory instructions have three uops, so they have to be
685 ;; read-modify-store instructions produce 4 uops so they have to be
H A Dhaswell.md612 ;; read-modify-store instructions produce 4 uops so they have to be
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedKryo.td16 // uops. Now, the latency spreadsheet has information based on fragmented uops,
20 let IssueWidth = 5; // 5-wide issue for expanded uops
H A DAArch64SchedFalkor.td19 let IssueWidth = 8; // 8 uops are dispatched per cycle.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMScheduleA8.td154 [1, 1, 1, 1, 3], [], -1>, // dynamic uops
159 [2, 1, 1, 1, 3], [], -1>, // dynamic uops
165 [1, 2, 1, 1, 3], [], -1>, // dynamic uops
170 [1, 1, 3], [], -1>, // dynamic uops
176 [1, 1, 3], [], -1>, // dynamic uops
232 [], [], -1>, // dynamic uops
237 [2], [], -1>, // dynamic uops
399 [1, 1, 1, 2], [], -1>, // dynamic uops
407 [2, 1, 1, 1, 2], [], -1>, // dynamic uops
427 [1, 1, 1, 1], [], -1>, // dynamic uops
[all …]
H A DARMScheduleA9.td287 -1>, // dynamic uops
296 -1>, // dynamic uops
306 -1>, // dynamic uops
315 -1>, // dynamic uops
325 -1>, // dynamic uops
420 [], [], -1>, // dynamic uops
427 [2], [], -1>, // dynamic uops
725 [1, 1, 1, 1], [], -1>, // dynamic uops
735 [2, 1, 1, 1], [], -1>, // dynamic uops
763 [1, 1, 1, 1], [], -1>, // dynamic uops
[all …]
H A DARMSchedule.td194 class BranchWriteRes<int lat, int uops, list<ProcResourceKind> resl,
199 let NumMicroOps = !add(wr.NumMicroOps, uops);
/netbsd-src/external/apache2/llvm/dist/llvm/docs/CommandGuide/
H A Dllvm-exegesis.rst46 $ llvm-exegesis -mode=uops -opcode-name=ADD64rr
82 To measure the latency/uops of a custom piece of code, you can specify the
87 $ echo "vzeroupper" | llvm-exegesis -mode=uops -snippets-file=-
118 Assuming you have a set of benchmarked instructions (either latency or uops) as
186 .. option:: -mode=[latency|uops|inverse_throughput|analysis]
236 File to read (`analysis` mode) or write (`latency`/`uops`/`inverse_throughput`
/netbsd-src/external/gpl3/gcc/dist/gcc/config/aarch64/
H A Dthunderx2t99.md94 ; Plain register moves are handled by renaming, and don't create any uops.
391 ; insns are split into uops, and those may be issued out-of-order).
H A Dthunderx3t110.md110 ; and don't create any uops.
535 ; necessarily accurate (because insns are split into uops, and those
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/
H A Dthunderx2t99.md94 ; Plain register moves are handled by renaming, and don't create any uops.
391 ; insns are split into uops, and those may be issued out-of-order).
H A Dthunderx3t110.md110 ; and don't create any uops.
535 ; necessarily accurate (because insns are split into uops, and those
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86SchedSkylakeServer.td2195 let NumMicroOps = 5; // 2 uops perform multiple loads
2204 let NumMicroOps = 5; // 2 uops perform multiple loads
2214 let NumMicroOps = 5; // 2 uops perform multiple loads
2224 let NumMicroOps = 5; // 2 uops perform multiple loads
2259 let NumMicroOps = 5; // 2 uops perform multiple loads
2268 let NumMicroOps = 5; // 2 uops peform multiple loads
2278 let NumMicroOps = 5; // 2 uops perform multiple loads
2458 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
2459 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86SchedSkylakeClient.td1601 let NumMicroOps = 5; // 2 uops perform multiple loads
1610 let NumMicroOps = 5; // 2 uops peform multiple loads
1620 let NumMicroOps = 5; // 2 uops perform multiple loads
1755 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1756 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86SchedSandyBridge.td1118 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1119 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
H A DX86ScheduleZnver1.td333 …esFpuPair<WriteFRnd, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops?
334 …esFpuPair<WriteFRndY, [ZnFPU3], 4, [1], 1, 7, 1>; // FIXME: Should folds require 1 extra uops?
H A DX86SchedBroadwell.td1605 // echo 'pxor %mm0, %mm0' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
1606 // echo 'vxorpd %xmm0, %xmm0, %xmm1' | /tmp/llvm-exegesis -mode=uops -snippets-file=-
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp340 unsigned uops = SchedModel->getNumMicroOps(SU->getInstr()); in checkHazard() local
341 if (IssueCount + uops > SchedModel->getIssueWidth()) in checkHazard()
/netbsd-src/external/lgpl3/gmp/dist/mpn/x86/p6/mmx/
H A Ddivrem_1.asm686 C uops

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