Home
last modified time | relevance | path

Searched refs:uint8_t (Results 1 – 25 of 5054) sorted by relevance

12345678910>>...203

/netbsd-src/sys/dev/ic/
H A Dspdmemvar.h52 uint8_t fpm_len;
53 uint8_t fpm_size;
54 uint8_t fpm_type;
55 uint8_t fpm_rows;
56 uint8_t fpm_cols;
57 uint8_t fpm_banks;
59 uint8_t fpm_voltage;
60 uint8_t fpm_tRAC;
61 uint8_t fpm_tCAC;
62 uint8_t fpm_config;
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_dp_types.h107 uint8_t link_rate_set;
139 uint8_t MINOR:4;
140 uint8_t MAJOR:4;
142 uint8_t raw;
147 uint8_t MAX_LANE_COUNT:5;
148 uint8_t POST_LT_ADJ_REQ_SUPPORTED:1;
149 uint8_t TPS3_SUPPORTED:1;
150 uint8_t ENHANCED_FRAME_CAP:1;
152 uint8_t raw;
157 uint8_t MAX_DOWN_SPREAD:1;
[all …]
/netbsd-src/external/bsd/unbound/dist/testcode/
H A Dunitdname.c105 unit_assert(query_dname_compare((uint8_t*)"", (uint8_t*)"") == 0); in dname_test_query_dname_compare()
106 unit_assert(query_dname_compare((uint8_t*)"\001a", in dname_test_query_dname_compare()
107 (uint8_t*)"\001a") == 0); in dname_test_query_dname_compare()
108 unit_assert(query_dname_compare((uint8_t*)"\003abc\001a", in dname_test_query_dname_compare()
109 (uint8_t*)"\003abc\001a") == 0); in dname_test_query_dname_compare()
110 unit_assert(query_dname_compare((uint8_t*)"\003aBc\001a", in dname_test_query_dname_compare()
111 (uint8_t*)"\003AbC\001A") == 0); in dname_test_query_dname_compare()
112 unit_assert(query_dname_compare((uint8_t*)"\003abc", in dname_test_query_dname_compare()
113 (uint8_t*)"\003abc\001a") == -1); in dname_test_query_dname_compare()
114 unit_assert(query_dname_compare((uint8_t*)"\003abc\001a", in dname_test_query_dname_compare()
[all …]
/netbsd-src/sys/arch/hp300/dev/
H A Ddvboxreg.h53 uint8_t :8, :8, :8;
54 uint8_t red;
55 uint8_t :8, :8, :8;
56 uint8_t green;
57 uint8_t :8, :8, :8;
58 uint8_t blue;
63 uint8_t f2[16359];
64 uint8_t wbusy; /* Window move in progress 0x4047 */
65 uint8_t f3[0x405b-0x4047-1];
66 uint8_t as_busy; /* Scan accessing frame buf. 0x405B */
[all …]
/netbsd-src/sys/dev/scsipi/
H A Dscsi_spc.h79 uint8_t opcode;
80 uint8_t byte2;
83 uint8_t reserved[2];
84 uint8_t length;
85 uint8_t control;
90 uint8_t opcode;
91 uint8_t byte2; /* see MODE SELECT (6) */
92 uint8_t reserved[5];
93 uint8_t length[2];
94 uint8_t control;
[all …]
H A Dscsipi_cd.h110 uint8_t length[2];
111 uint8_t first; /* track or session */
112 uint8_t last;
117 uint8_t unused1;
118 uint8_t adrcontrol;
119 uint8_t tracknr;
120 uint8_t unused2;
121 uint8_t msf_lba[4]; /* union msf_lba from cdio.h */
126 uint8_t unused1;
127 uint8_t adrcontol;
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/
H A Datomfirmware.h54 #ifndef uint8_t
55 typedef unsigned char uint8_t; typedef
230 …uint8_t format_revision; //mainly used for a hw function, when the parser is not backward compa…
231 …uint8_t content_revision; //change it when a data table has a structure change, or a hw function…
240 …uint8_t atom_bios_string[4]; //enum atom_string_def atom_bios_string; //Signature to d…
443 uint8_t h_border;
444 uint8_t v_border;
446 uint8_t atom_mode_id;
447 uint8_t refreshrate;
486 uint8_t mem_module_id;
[all …]
/netbsd-src/sys/dev/
H A Dsmbiosvar.h46 uint8_t rev;
47 uint8_t mjr;
48 uint8_t min;
49 uint8_t doc;
50 uint8_t *addr;
57 uint8_t checksum; /* Entry point checksum */
58 uint8_t len; /* Entry point structure length */
59 uint8_t majrev; /* Specification major revision */
60 uint8_t minrev; /* Specification minor revision */
62 uint8_t epr; /* Entry Point Revision */
[all …]
H A Dipmivar.h72 int (*sendmsg)(struct ipmi_softc *, int, const uint8_t *);
73 int (*recvmsg)(struct ipmi_softc *, int, int *, uint8_t *);
134 uint8_t deviceid;
135 uint8_t revision;
136 uint8_t fwrev1;
137 uint8_t fwrev2;
138 uint8_t version;
139 uint8_t additional;
140 uint8_t manufacturer[3];
141 uint8_t produc
[all...]
/netbsd-src/sys/stand/efiboot/
H A Dsmbios.h41 uint8_t rev;
42 uint8_t mjr;
43 uint8_t min;
44 uint8_t doc;
45 uint8_t *addr;
52 uint8_t checksum; /* Entry point checksum */
53 uint8_t len; /* Entry point structure length */
54 uint8_t majrev; /* Specification major revision */
55 uint8_t minrev; /* Specification minor revision */
57 uint8_t epr; /* Entry Point Revision */
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dsmu7_fusion.h48 uint8_t DisplayPhy1Config;
49 uint8_t DisplayPhy2Config;
50 uint8_t DisplayPhy3Config;
51 uint8_t DisplayPhy4Config;
53 uint8_t DisplayPhy5Config;
54 uint8_t DisplayPhy6Config;
55 uint8_t DisplayPhy7Config;
56 uint8_t DisplayPhy8Config;
62 uint8_t SClkDpmEnabledLevels;
63 uint8_t MClkDpmEnabledLevels;
[all …]
H A Dsmu7_discrete.h57 uint8_t DisplayPhy1Config;
58 uint8_t DisplayPhy2Config;
59 uint8_t DisplayPhy3Config;
60 uint8_t DisplayPhy4Config;
62 uint8_t DisplayPhy5Config;
63 uint8_t DisplayPhy6Config;
64 uint8_t DisplayPhy7Config;
65 uint8_t DisplayPhy8Config;
71 uint8_t SClkDpmEnabledLevels;
72 uint8_t MClkDpmEnabledLevels;
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/
H A Dsmu7_fusion.h48 uint8_t DisplayPhy1Config;
49 uint8_t DisplayPhy2Config;
50 uint8_t DisplayPhy3Config;
51 uint8_t DisplayPhy4Config;
53 uint8_t DisplayPhy5Config;
54 uint8_t DisplayPhy6Config;
55 uint8_t DisplayPhy7Config;
56 uint8_t DisplayPhy8Config;
62 uint8_t SClkDpmEnabledLevels;
63 uint8_t MClkDpmEnabledLevels;
[all …]
H A Dsmu74_discrete.h46 uint8_t vco_setting;
47 uint8_t postdiv;
57 uint8_t Smio;
58 uint8_t padding;
74 uint8_t PllRange;
75 uint8_t SSc_En;
87 uint8_t pcieDpmLevel;
88 uint8_t DeepSleepDivId;
94 uint8_t SclkDid;
95 uint8_t padding;
[all …]
H A Dsmu73_discrete.h35 uint8_t Smio;
36 uint8_t padding;
53 uint8_t pcieDpmLevel;
54 uint8_t DeepSleepDivId;
62 uint8_t SclkDid;
63 uint8_t DisplayWatermark;
64 uint8_t EnabledForActivity;
65 uint8_t EnabledForThrottle;
66 uint8_t UpHyst;
67 uint8_t DownHyst;
[all …]
H A Dsmu75_discrete.h45 uint8_t vco_setting; /* 1: 3-6GHz, 3: 2-4GHz */
46 uint8_t postdiv; /* divide by 2^n */
55 uint8_t Smio;
56 uint8_t padding;
72 uint8_t PllRange;
73 uint8_t SSc_En;
86 uint8_t pcieDpmLevel;
87 uint8_t DeepSleepDivId;
95 uint8_t SclkDid;
96 uint8_t padding;
[all …]
H A Dsmu71_discrete.h43 uint8_t Smio;
44 uint8_t padding;
56 uint8_t pcieDpmLevel;
57 uint8_t DeepSleepDivId;
66 uint8_t SclkDid;
67 uint8_t DisplayWatermark;
68 uint8_t EnabledForActivity;
69 uint8_t EnabledForThrottle;
70 uint8_t UpHyst;
71 uint8_t DownHyst;
[all …]
H A Dsmu7_discrete.h57 uint8_t DisplayPhy1Config;
58 uint8_t DisplayPhy2Config;
59 uint8_t DisplayPhy3Config;
60 uint8_t DisplayPhy4Config;
62 uint8_t DisplayPhy5Config;
63 uint8_t DisplayPhy6Config;
64 uint8_t DisplayPhy7Config;
65 uint8_t DisplayPhy8Config;
71 uint8_t SClkDpmEnabledLevels;
72 uint8_t MClkDpmEnabledLevels;
[all …]
H A Dsmu72_discrete.h37 uint8_t Smio;
38 uint8_t padding;
54 uint8_t pcieDpmLevel;
55 uint8_t DeepSleepDivId;
64 uint8_t SclkDid;
65 uint8_t DisplayWatermark;
66 uint8_t EnabledForActivity;
67 uint8_t EnabledForThrottle;
68 uint8_t UpHyst;
69 uint8_t DownHyst;
[all …]
H A Dsmu9_driver_if.h86 uint8_t SsOn;
87 uint8_t Did; /* DID */
95 uint8_t a0_shift;
96 uint8_t a1_shift;
97 uint8_t a2_shift;
98 uint8_t padding;
106 uint8_t m1_shift;
107 uint8_t m2_shift;
108 uint8_t b_shift;
109 uint8_t padding;
[all …]
/netbsd-src/external/mit/xorg/lib/libxcb/files/
H A Dxkb.h333 uint8_t flags;
334 uint8_t whichGroups;
335 uint8_t groups;
336 uint8_t whichMods;
337 uint8_t mods;
338 uint8_t realMods;
405 uint8_t mask;
406 uint8_t realMods;
472 uint8_t active;
473 uint8_t mods_mask;
[all …]
/netbsd-src/usr.sbin/fstyp/
H A Dmsdosfs.h61 uint8_t BS_jmpBoot[3];
62 uint8_t BS_OEMName[8];
63 uint8_t BPB_BytsPerSec[2];
64 uint8_t BPB_SecPerClus;
65 uint8_t BPB_RsvdSecCnt[2];
66 uint8_t BPB_NumFATs;
67 uint8_t BPB_RootEntCnt[2];
68 uint8_t BPB_TotSec16[2];
69 uint8_t BPB_Media;
70 uint8_t BPB_FATSz16[2];
[all …]
/netbsd-src/external/bsd/pdisk/dist/
H A DMacSCSICommand.h42 uint8_t opcode; /* 0 */
43 uint8_t lbn3; /* 1 lbn in low 5 */
44 uint8_t lbn2; /* 2 */
45 uint8_t lbn1; /* 3 */
46 uint8_t len; /* 4 */
47 uint8_t ctrl; /* 5 */
52 uint8_t opcode; /* 0 */
53 uint8_t lun; /* 1 */
54 uint8_t lbn4; /* 2 */
55 uint8_t lbn3; /* 3 */
[all …]
/netbsd-src/sys/dev/pci/
H A Dtwareg.h249 uint8_t opcode:5; /* TWA_OP_INITCONNECTION */
250 uint8_t res1:3;
251 uint8_t size;
252 uint8_t request_id;
253 uint8_t res2;
254 uint8_t status;
255 uint8_t flags;
266 uint8_t opcode:5; /* TWA_DOWNLOAD_FIRMWARE */
267 uint8_t sgl_offset:3;
268 uint8_t size;
[all …]
/netbsd-src/sys/dev/sun/
H A Deeprom.h54 uint8_t eeTestArea[4]; /* Factory Defined */
56 uint8_t eeChecksum[4]; /* || || */
60 uint8_t eeInstalledMem; /* Megabytes */
61 uint8_t eeMemTestSize; /* || */
64 uint8_t eeScreenSize;
70 uint8_t eeWatchDogDoesReset; /* Watchdog timeout action:
75 uint8_t eeBootDevStored; /* Is the boot device stored:
81 uint8_t eeBootDevName[2]; /* xy,xd,sd,ie,le,st,xt,mt,... */
82 uint8_t eeBootDevCtlr;
83 uint8_t eeBootDevUnit;
[all …]

12345678910>>...203