Searched refs:ucRefClkSource (Results 1 – 5 of 5) sorted by relevance
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/ |
| H A D | amdgpu_atombios_encoders.c | 976 args.v3.acConfig.ucRefClkSource = 2; /* external src */ in amdgpu_atombios_encoder_setup_dig_transmitter()
978 args.v3.acConfig.ucRefClkSource = pll_id; in amdgpu_atombios_encoder_setup_dig_transmitter()
1036 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; in amdgpu_atombios_encoder_setup_dig_transmitter()
1038 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; in amdgpu_atombios_encoder_setup_dig_transmitter()
1040 args.v4.acConfig.ucRefClkSource = pll_id; in amdgpu_atombios_encoder_setup_dig_transmitter()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_atombios_encoders.c | 1230 args.v3.acConfig.ucRefClkSource = 2; /* external src */ in atombios_dig_transmitter_setup2()
1232 args.v3.acConfig.ucRefClkSource = pll_id; in atombios_dig_transmitter_setup2()
1290 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_EXTCLK; in atombios_dig_transmitter_setup2()
1292 args.v4.acConfig.ucRefClkSource = ENCODER_REFCLK_SRC_DCPLL; in atombios_dig_transmitter_setup2()
1294 args.v4.acConfig.ucRefClkSource = pll_id; in atombios_dig_transmitter_setup2()
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| H A D | atombios.h | 1097 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 member
1109 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1193 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New member
1205 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/bios/ |
| H A D | amdgpu_command_table.c | 645 params.acConfig.ucRefClkSource = (uint8_t)pll_id; in transmitter_control_v3()
769 params.acConfig.ucRefClkSource = (uint8_t)(ref_clk_src_id); in transmitter_control_v4()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/include/ |
| H A D | atombios.h | 1303 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2 member
1315 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, EXT_CLK=2
1399 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New member
1411 UCHAR ucRefClkSource:2; //bit5:4: PPLL1 =0, PPLL2=1, DCPLL=2, EXT_CLK=3 <= New
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