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Searched refs:train_set (Results 1 – 6 of 6) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_dp_link_training.c71 intel_dp->train_set[lane] = v | p; in intel_get_adjust_train()
78 u8 buf[sizeof(intel_dp->train_set) + 1]; in intel_dp_set_link_train()
90 memcpy(buf + 1, intel_dp->train_set, intel_dp->lane_count); in intel_dp_set_link_train()
104 memset(intel_dp->train_set, 0, sizeof(intel_dp->train_set)); in intel_dp_reset_link_train()
117 intel_dp->train_set, intel_dp->lane_count); in intel_dp_update_link_train()
127 if ((intel_dp->train_set[lane] & in intel_dp_link_max_vswing_reached()
220 voltage = intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in intel_dp_link_training_clock_recovery()
229 if ((intel_dp->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == in intel_dp_link_training_clock_recovery()
H A Dintel_dp.c3879 u8 train_set = intel_dp->train_set[0]; in vlv_signal_levels() local
3881 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in vlv_signal_levels()
3884 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3907 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3926 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3941 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in vlv_signal_levels()
3965 u8 train_set = intel_dp->train_set[0]; in chv_signal_levels() local
3967 switch (train_set & DP_TRAIN_PRE_EMPHASIS_MASK) { in chv_signal_levels()
3969 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_signal_levels()
3992 switch (train_set & DP_TRAIN_VOLTAGE_SWING_MASK) { in chv_signal_levels()
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H A Dintel_display_types.h1258 u8 train_set[4]; member
H A Dintel_ddi.c2906 u8 train_set = intel_dp->train_set[0]; in intel_ddi_dp_level() local
2907 int signal_levels = train_set & (DP_TRAIN_VOLTAGE_SWING_MASK | in intel_ddi_dp_level()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_atombios_dp.c213 u8 train_set[4]) in amdgpu_atombios_dp_get_adjust_train()
245 train_set[lane] = v | p; in amdgpu_atombios_dp_get_adjust_train()
488 u8 train_set[4]; member
500 0, dp_info->train_set[0]); /* sets all lanes at once */ in amdgpu_atombios_dp_update_vs_emph()
504 dp_info->train_set, dp_info->dp_lane_count); in amdgpu_atombios_dp_update_vs_emph()
598 memset(dp_info->train_set, 0, 4); in amdgpu_atombios_dp_link_train_cr()
622 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in amdgpu_atombios_dp_link_train_cr()
630 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in amdgpu_atombios_dp_link_train_cr()
639 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in amdgpu_atombios_dp_link_train_cr()
643 dp_info->train_set); in amdgpu_atombios_dp_link_train_cr()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_atombios_dp.c271 u8 train_set[4]) in dp_get_adjust_train()
303 train_set[lane] = v | p; in dp_get_adjust_train()
558 u8 train_set[4]; member
570 0, dp_info->train_set[0]); /* sets all lanes at once */ in radeon_dp_update_vs_emph()
574 dp_info->train_set, dp_info->dp_lane_count); in radeon_dp_update_vs_emph()
685 memset(dp_info->train_set, 0, 4); in radeon_dp_link_train_cr()
709 if ((dp_info->train_set[i] & DP_TRAIN_MAX_SWING_REACHED) == 0) in radeon_dp_link_train_cr()
717 if ((dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK) == voltage) { in radeon_dp_link_train_cr()
726 voltage = dp_info->train_set[0] & DP_TRAIN_VOLTAGE_SWING_MASK; in radeon_dp_link_train_cr()
729 dp_get_adjust_train(dp_info->link_status, dp_info->dp_lane_count, dp_info->train_set); in radeon_dp_link_train_cr()
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