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Searched refs:tg (Results 1 – 25 of 117) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_timing_generator.c71 struct timing_generator *tg, in dce110_timing_generator_apply_front_porch_workaround() argument
97 struct timing_generator *tg) in dce110_timing_generator_is_in_vertical_blank() argument
102 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_is_in_vertical_blank()
105 value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_is_in_vertical_blank()
111 struct timing_generator *tg, in dce110_timing_generator_set_early_control() argument
115 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_set_early_control()
118 regval = dm_read_reg(tg->ctx, address); in dce110_timing_generator_set_early_control()
121 dm_write_reg(tg->ctx, address, regval); in dce110_timing_generator_set_early_control()
128 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_enable_crtc() argument
132 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce110_timing_generator_enable_crtc()
[all …]
H A Ddce110_timing_generator.h119 #define DCE110TG_FROM_TG(tg)\ argument
120 container_of(tg, struct dce110_timing_generator, base)
123 struct dce110_timing_generator *tg,
130 struct timing_generator *tg,
138 struct timing_generator *tg,
142 bool dce110_timing_generator_enable_crtc(struct timing_generator *tg);
143 bool dce110_timing_generator_disable_crtc(struct timing_generator *tg);
146 struct timing_generator *tg,
153 struct timing_generator *tg);
156 struct timing_generator *tg,
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H A Damdgpu_dce110_timing_generator_v.c47 tg->ctx->logger
58 static bool dce110_timing_generator_v_enable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_enable_crtc() argument
70 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
75 dm_write_reg(tg->ctx, mmCRTCV_MASTER_UPDATE_MODE, value); in dce110_timing_generator_v_enable_crtc()
80 dm_write_reg(tg->ctx, in dce110_timing_generator_v_enable_crtc()
86 static bool dce110_timing_generator_v_disable_crtc(struct timing_generator *tg) in dce110_timing_generator_v_disable_crtc() argument
90 value = dm_read_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
96 dm_write_reg(tg->ctx, in dce110_timing_generator_v_disable_crtc()
105 static void dce110_timing_generator_v_blank_crtc(struct timing_generator *tg) in dce110_timing_generator_v_blank_crtc() argument
108 uint32_t value = dm_read_reg(tg->ctx, addr); in dce110_timing_generator_v_blank_crtc()
[all …]
H A Damdgpu_dce110_hw_sequencer.c667 struct timing_generator *tg = pipe_ctx->stream_res.tg; in dce110_enable_stream() local
690 tg->funcs->set_early_control(tg, early_control); in dce110_enable_stream()
1185 pipe_ctx->stream_res.tg->inst + 1); in build_audio_output()
1197 uint32_t color_value = MAX_TG_COLOR_VALUE * (4 - pipe_ctx->stream_res.tg->inst) / 4; in get_surface_visual_confirm_color()
1252 if (pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color) { in program_scaler()
1261 pipe_ctx->stream_res.tg->funcs->set_overscan_blank_color( in program_scaler()
1262 pipe_ctx->stream_res.tg, in program_scaler()
1285 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_enable_stream_timing()
1286 pipe_ctx->stream_res.tg, in dce110_enable_stream_timing()
1293 pipe_ctx->stream_res.tg->funcs->set_blank(pipe_ctx->stream_res.tg, true); in dce110_enable_stream_timing()
[all …]
H A Damdgpu_dce110_resource.c873 pixel_clk_params->controller_id = pipe_ctx->stream_res.tg->inst + 1; in get_pixel_clock_parameters()
1113 pipe_ctx->stream_res.tg = pool->timing_generators[underlay_idx]; in dce110_acquire_underlay()
1128 pipe_ctx->stream_res.tg->inst, in dce110_acquire_underlay()
1136 pipe_ctx->stream_res.tg->funcs->program_timing(pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1145 pipe_ctx->stream_res.tg->funcs->enable_advanced_request( in dce110_acquire_underlay()
1146 pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
1158 pipe_ctx->stream_res.tg->funcs->set_blank_color( in dce110_acquire_underlay()
1159 pipe_ctx->stream_res.tg, in dce110_acquire_underlay()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
H A Dtiming_generator.h139 bool (*validate_timing)(struct timing_generator *tg,
141 void (*program_timing)(struct timing_generator *tg,
161 bool (*enable_crtc)(struct timing_generator *tg);
162 bool (*disable_crtc)(struct timing_generator *tg);
163 bool (*is_counter_moving)(struct timing_generator *tg);
164 void (*get_position)(struct timing_generator *tg,
167 uint32_t (*get_frame_count)(struct timing_generator *tg);
169 struct timing_generator *tg,
177 bool (*is_matching_timing)(struct timing_generator *tg,
179 void (*set_early_control)(struct timing_generator *tg,
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce120/
H A Damdgpu_dce120_timing_generator.c91 struct timing_generator *tg) in dce120_timing_generator_is_in_vertical_blank() argument
94 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_is_in_vertical_blank()
96 tg->ctx, in dce120_timing_generator_is_in_vertical_blank()
107 struct timing_generator *tg, in dce120_timing_generator_validate_timing() argument
116 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_validate_timing()
119 tg, in dce120_timing_generator_validate_timing()
133 bool dce120_tg_validate_timing(struct timing_generator *tg, in dce120_tg_validate_timing() argument
136 return dce120_timing_generator_validate_timing(tg, timing, SIGNAL_TYPE_NONE); in dce120_tg_validate_timing()
141 bool dce120_timing_generator_enable_crtc(struct timing_generator *tg) in dce120_timing_generator_enable_crtc() argument
144 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce120_timing_generator_enable_crtc()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hw_sequencer.c95 struct timing_generator *tg; in dcn10_lock_all_pipes() local
100 tg = pipe_ctx->stream_res.tg; in dcn10_lock_all_pipes()
107 !tg->funcs->is_tg_enabled(tg)) in dcn10_lock_all_pipes()
111 tg->funcs->lock(tg); in dcn10_lock_all_pipes()
113 tg->funcs->unlock(tg); in dcn10_lock_all_pipes()
346 struct timing_generator *tg = pool->timing_generators[i]; in dcn10_log_hw_state() local
349 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_log_hw_state()
361 s.blank_enabled = tg->funcs->is_blanked(tg); in dcn10_log_hw_state()
368 tg->inst, in dcn10_log_hw_state()
392 tg->funcs->clear_optc_underflow(tg); in dcn10_log_hw_state()
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H A Damdgpu_dcn10_hw_sequencer_debug.c432 struct timing_generator *tg = pool->timing_generators[i]; in dcn10_get_otg_states() local
436 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_get_otg_states()
444 tg->inst, in dcn10_get_otg_states()
499 struct timing_generator *tg = pool->timing_generators[i]; in dcn10_clear_otpc_underflow() local
502 optc1_read_otg_state(DCN10TG_FROM_TG(tg), &s); in dcn10_clear_otpc_underflow()
505 tg->funcs->clear_optc_underflow(tg); in dcn10_clear_otpc_underflow()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_hwseq.c165 if (pipe_ctx->stream_res.tg->funcs->set_gsl != NULL && in dcn20_setup_gsl_group_as_lock()
166 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select != NULL) { in dcn20_setup_gsl_group_as_lock()
167 pipe_ctx->stream_res.tg->funcs->set_gsl( in dcn20_setup_gsl_group_as_lock()
168 pipe_ctx->stream_res.tg, in dcn20_setup_gsl_group_as_lock()
171 pipe_ctx->stream_res.tg->funcs->set_gsl_source_select( in dcn20_setup_gsl_group_as_lock()
172 pipe_ctx->stream_res.tg, group_idx, enable ? 4 : 0); in dcn20_setup_gsl_group_as_lock()
278 struct timing_generator *tg) in dcn20_init_blank() argument
293 tg->funcs->get_otg_active_size(tg, in dcn20_init_blank()
298 tg->funcs->get_optc_source(tg, &num_opps, &opp_id_src0, &opp_id_src1); in dcn20_init_blank()
635 pipe_ctx->stream_res.tg->funcs->set_odm_combine( in dcn20_enable_stream_timing()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce80/
H A Damdgpu_dce80_timing_generator.c92 static void program_pix_dur(struct timing_generator *tg, uint32_t pix_clk_100hz) in program_pix_dur() argument
96 + DCE110TG_FROM_TG(tg)->offsets.dmif; in program_pix_dur()
97 uint32_t value = dm_read_reg(tg->ctx, addr); in program_pix_dur()
110 dm_write_reg(tg->ctx, addr, value); in program_pix_dur()
113 static void program_timing(struct timing_generator *tg, in program_timing() argument
123 program_pix_dur(tg, timing->pix_clk_100hz); in program_timing()
125 dce110_tg_program_timing(tg, timing, 0, 0, 0, 0, 0, use_vbios); in program_timing()
129 struct timing_generator *tg, in dce80_timing_generator_enable_advanced_request() argument
133 struct dce110_timing_generator *tg110 = DCE110TG_FROM_TG(tg); in dce80_timing_generator_enable_advanced_request()
135 uint32_t value = dm_read_reg(tg->ctx, addr); in dce80_timing_generator_enable_advanced_request()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_hwseq.c61 if (lock && pipe->stream_res.tg->funcs->is_blanked && in dce_pipe_control_lock()
62 pipe->stream_res.tg->funcs->is_blanked(pipe->stream_res.tg)) in dce_pipe_control_lock()
65 val = REG_GET_4(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], in dce_pipe_control_lock()
76 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
81 REG_SET_2(BLND_V_UPDATE_LOCK[pipe->stream_res.tg->inst], val, in dce_pipe_control_lock()
87 uint32_t value = REG_READ(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst]); in dce_pipe_control_lock()
88 REG_WRITE(CRTC_H_BLANK_START_END[pipe->stream_res.tg->inst], value); in dce_pipe_control_lock()
/netbsd-src/external/apache2/llvm/dist/clang/utils/
H A DFuzzTest72 def __init__(self, tg, test): argument
73 self.tg = tg
81 name,data = self.tg.inputs[i]
95 name,data = self.tg.inputs[i]
114 file_data = test_application.tg.inputs[test[3][0]][1]
319 tg = TestGenerator(input_files, opts.enable_delete, opts.enable_insert,
322 print '%s: note: %d input bytes.' % (sys.argv[0], tg.num_positions)
323 print '%s: note: %d total tests.' % (sys.argv[0], tg.num_tests)
328 itertools.repeat(tg.num_tests, opts.max_tests))
330 it = itertools.imap(random.randrange, itertools.repeat(tg.num_tests))
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/netbsd-src/sys/external/bsd/drm2/dist/drm/
H A Ddrm_connector.c2321 struct drm_tile_group *tg = container_of(kref, struct drm_tile_group, refcount); in drm_tile_group_free() local
2322 struct drm_device *dev = tg->dev; in drm_tile_group_free()
2324 idr_remove(&dev->mode_config.tile_idr, tg->id); in drm_tile_group_free()
2326 kfree(tg); in drm_tile_group_free()
2337 struct drm_tile_group *tg) in drm_mode_put_tile_group() argument
2339 kref_put(&tg->refcount, drm_tile_group_free); in drm_mode_put_tile_group()
2356 struct drm_tile_group *tg; in drm_mode_get_tile_group() local
2359 idr_for_each_entry(&dev->mode_config.tile_idr, tg, id) { in drm_mode_get_tile_group()
2360 if (!memcmp(tg->group_data, topology, 8)) { in drm_mode_get_tile_group()
2361 if (!kref_get_unless_zero(&tg->refcount)) in drm_mode_get_tile_group()
[all …]
/netbsd-src/sbin/routed/
H A Dparms.c592 struct tgate *tg; in parse_parms() local
822 tg = (struct tgate *)rtmalloc(sizeof(*tg), in parse_parms()
825 memset(tg, 0, sizeof(*tg)); in parse_parms()
826 tg->tgate_addr = addr; in parse_parms()
834 || !getnet(buf2, &tg->tgate_nets[i].net, in parse_parms()
835 &tg->tgate_nets[i].mask) in parse_parms()
836 || tg->tgate_nets[i].net == RIP_DEFAULT in parse_parms()
837 || tg->tgate_nets[i].mask == 0) { in parse_parms()
838 free(tg); in parse_parms()
843 tg->tgate_next = tgates; in parse_parms()
[all …]
H A Dinput.c155 struct tgate *tg = 0; in input() local
582 tg = tgates; in input()
583 while (tg->tgate_addr != FROM_NADDR) { in input()
584 tg = tg->tgate_next; in input()
585 if (tg == 0) { in input()
685 if (tg && (tn = tg->tgate_nets)->mask != 0) { in input()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_hw_sequencer.c278 struct timing_generator *tg) in hwss_wait_for_blank_complete() argument
283 if (!tg->funcs->is_blanked) in hwss_wait_for_blank_complete()
286 if (tg->funcs->is_blanked(tg)) in hwss_wait_for_blank_complete()
H A Damdgpu_dc_stream.c516 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_vblank_counter() local
521 return tg->funcs->get_frame_count(tg); in dc_stream_get_vblank_counter()
575 struct timing_generator *tg = res_ctx->pipe_ctx[i].stream_res.tg; in dc_stream_get_scanoutpos() local
580 tg->funcs->get_scanoutpos(tg, in dc_stream_get_scanoutpos()
H A Damdgpu_dc.c294 if (pipe->stream == stream && pipe->stream_res.tg) { in dc_stream_adjust_vmin_vmax()
350 struct timing_generator *tg; in dc_stream_configure_crc() local
376 tg = pipe->stream_res.tg; in dc_stream_configure_crc()
379 if (tg->funcs->configure_crc) in dc_stream_configure_crc()
380 return tg->funcs->configure_crc(tg, &param); in dc_stream_configure_crc()
399 struct timing_generator *tg; in dc_stream_get_crc() local
410 tg = pipe->stream_res.tg; in dc_stream_get_crc()
412 if (tg->funcs->get_crc) in dc_stream_get_crc()
413 return tg->funcs->get_crc(tg, r_cr, g_y, b_cb); in dc_stream_get_crc()
1049 struct timing_generator *tg; in dc_validate_seamless_boot_timing() local
[all …]
H A Damdgpu_dc_link_hwss.c467 DC_LOG_DSC("Setting optc DSC config for tg instance %d:", pipe_ctx->stream_res.tg->inst); in dp_set_dsc_on_stream()
469 pipe_ctx->stream_res.tg->funcs->set_dsc_config(pipe_ctx->stream_res.tg, in dp_set_dsc_on_stream()
475 pipe_ctx->stream_res.tg->funcs->set_dsc_config( in dp_set_dsc_on_stream()
476 pipe_ctx->stream_res.tg, in dp_set_dsc_on_stream()
H A Damdgpu_dc_debug.c331 pipe_ctx->stream_res.tg->funcs->get_position(pipe_ctx->stream_res.tg, &position); in context_timing_trace()
342 pipe_ctx->stream_res.tg->inst, in context_timing_trace()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
H A Damdgpu_irq_service_dce110.c219 struct timing_generator *tg = in dce110_vblank_set() local
220 dc->current_state->res_ctx.pipe_ctx[pipe_offset].stream_res.tg; in dce110_vblank_set()
223 if (!tg || !tg->funcs->arm_vert_intr(tg, 2)) { in dce110_vblank_set()
/netbsd-src/external/gpl3/gcc/dist/libphobos/src/std/experimental/allocator/building_blocks/
H A Daligned_block_list.d561 auto tg = new ThreadGroup; variable
564 tg.create(&fun);
566 tg.joinAll();
624 auto tg = new ThreadGroup; variable
627 tg.create(&fun);
629 tg.joinAll();
H A Dascending_page_allocator.d658 auto tg = new ThreadGroup; variable
661 tg.create(&fun);
663 tg.joinAll();
951 auto tg = new ThreadGroup; variable
954 tg.create(&fun);
956 tg.joinAll();
995 auto tg = new ThreadGroup; variable
998 tg.create(&fun);
1000 tg.joinAll();
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DTimer.h97 Timer(StringRef TimerName, StringRef TimerDescription, TimerGroup &tg) { in Timer() argument
98 init(TimerName, TimerDescription, tg); in Timer()
112 void init(StringRef TimerName, StringRef TimerDescription, TimerGroup &tg);

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