Searched refs:shift5 (Results 1 – 4 of 4) sorted by relevance
| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/ |
| H A D | amdgpu_dc_helper.c | 380 uint8_t shift5, uint32_t mask5, uint32_t *field_value5) in generic_reg_get5() argument
387 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); in generic_reg_get5()
396 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, in generic_reg_get6() argument
404 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); in generic_reg_get6()
414 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, in generic_reg_get7() argument
423 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); in generic_reg_get7()
434 uint8_t shift5, uint32_t mask5, uint32_t *field_value5, in generic_reg_get8() argument
444 *field_value5 = get_reg_field_value_ex(reg_val, mask5, shift5); in generic_reg_get8()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/ |
| H A D | reg_helper.h | 416 uint8_t shift5, uint32_t mask5, uint32_t *field_value5);
423 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
431 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
440 uint8_t shift5, uint32_t mask5, uint32_t *field_value5,
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/tilepro/ |
| H A D | gen-mul-tables.cc | 313 Operator ("CODE_FOR_ashlsi3", "shli", shift5, 5, 1005),
355 Operator ("CODE_FOR_ashldi3", "shli", shift5, 5, 1005),
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/tilepro/ |
| H A D | gen-mul-tables.cc | 313 Operator ("CODE_FOR_ashlsi3", "shli", shift5, 5, 1005),
355 Operator ("CODE_FOR_ashldi3", "shli", shift5, 5, 1005),
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