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Searched refs:set_wptr (Results 1 – 25 of 27) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_asic.c200 .set_wptr = &r100_gfx_set_wptr,
350 .set_wptr = &r100_gfx_set_wptr,
364 .set_wptr = &r100_gfx_set_wptr,
921 .set_wptr = &r600_gfx_set_wptr,
934 .set_wptr = &r600_dma_set_wptr,
1019 .set_wptr = &uvd_v1_0_set_wptr,
1222 .set_wptr = &uvd_v1_0_set_wptr,
1331 .set_wptr = &r600_gfx_set_wptr,
1344 .set_wptr = &r600_dma_set_wptr,
1646 .set_wptr = &cayman_gfx_set_wptr,
[all …]
H A Dradeon.h1861 void (*set_wptr)(struct radeon_device *rdev, struct radeon_ring *ring); member
2803 #define radeon_ring_set_wptr(rdev, r) (rdev)->asic->ring[(r)->idx]->set_wptr((rdev), (r))
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_ring.h128 void (*set_wptr)(struct amdgpu_ring *ring); member
241 #define amdgpu_ring_set_wptr(r) (r)->funcs->set_wptr((r))
H A Damdgpu_vce_v3_0.c905 .set_wptr = vce_v3_0_ring_set_wptr,
929 .set_wptr = vce_v3_0_ring_set_wptr,
H A Damdgpu_uvd_v6_0.c1527 .set_wptr = uvd_v6_0_ring_set_wptr,
1553 .set_wptr = uvd_v6_0_ring_set_wptr,
1582 .set_wptr = uvd_v6_0_enc_ring_set_wptr,
H A Damdgpu_vce_v2_0.c616 .set_wptr = vce_v2_0_ring_set_wptr,
H A Damdgpu_sdma_v4_0.c2258 .set_wptr = sdma_v4_0_ring_set_wptr,
2294 .set_wptr = sdma_v4_0_ring_set_wptr,
2326 .set_wptr = sdma_v4_0_page_ring_set_wptr,
2358 .set_wptr = sdma_v4_0_page_ring_set_wptr,
H A Damdgpu_jpeg_v2_5.c583 .set_wptr = jpeg_v2_5_dec_ring_set_wptr,
H A Damdgpu_jpeg_v1_0.c552 .set_wptr = jpeg_v1_0_decode_ring_set_wptr,
H A Damdgpu_uvd_v4_2.c752 .set_wptr = uvd_v4_2_ring_set_wptr,
H A Damdgpu_jpeg_v2_0.c784 .set_wptr = jpeg_v2_0_dec_ring_set_wptr,
H A Damdgpu_uvd_v5_0.c861 .set_wptr = uvd_v5_0_ring_set_wptr,
H A Damdgpu_vcn_v2_0.c1716 .set_wptr = vcn_v2_0_dec_ring_set_wptr,
1747 .set_wptr = vcn_v2_0_enc_ring_set_wptr,
H A Damdgpu_si_dma.c731 .set_wptr = si_dma_ring_set_wptr,
H A Damdgpu_uvd_v7_0.c1787 .set_wptr = uvd_v7_0_ring_set_wptr,
1820 .set_wptr = uvd_v7_0_enc_ring_set_wptr,
H A Damdgpu_vcn_v1_0.c1884 .set_wptr = vcn_v1_0_dec_ring_set_wptr,
1918 .set_wptr = vcn_v1_0_enc_ring_set_wptr,
H A Damdgpu_vcn_v2_5.c1490 .set_wptr = vcn_v2_5_dec_ring_set_wptr,
1590 .set_wptr = vcn_v2_5_enc_ring_set_wptr,
H A Damdgpu_sdma_v2_4.c1148 .set_wptr = sdma_v2_4_ring_set_wptr,
H A Damdgpu_vce_v4_0.c1083 .set_wptr = vce_v4_0_ring_set_wptr,
H A Damdgpu_cik_sdma.c1260 .set_wptr = cik_sdma_ring_set_wptr,
H A Damdgpu_sdma_v3_0.c1586 .set_wptr = sdma_v3_0_ring_set_wptr,
H A Damdgpu_sdma_v5_0.c1597 .set_wptr = sdma_v5_0_ring_set_wptr,
H A Damdgpu_gfx_v6_0.c3498 .set_wptr = gfx_v6_0_ring_set_wptr_gfx,
3523 .set_wptr = gfx_v6_0_ring_set_wptr_compute,
H A Damdgpu_gfx_v10_0.c5159 .set_wptr = gfx_v10_0_ring_set_wptr_gfx,
5211 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
5245 .set_wptr = gfx_v10_0_ring_set_wptr_compute,
H A Damdgpu_gfx_v7_0.c5014 .set_wptr = gfx_v7_0_ring_set_wptr_gfx,
5046 .set_wptr = gfx_v7_0_ring_set_wptr_compute,

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