| /netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/ |
| H A D | radeon_asic.c | 242 .set_reg = r100_set_surface_reg,
310 .set_reg = r100_set_surface_reg,
406 .set_reg = r100_set_surface_reg,
474 .set_reg = r100_set_surface_reg,
542 .set_reg = r100_set_surface_reg,
610 .set_reg = r100_set_surface_reg,
678 .set_reg = r100_set_surface_reg,
746 .set_reg = r100_set_surface_reg,
814 .set_reg = r100_set_surface_reg,
882 .set_reg = r100_set_surface_reg,
[all …]
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| H A D | radeon.h | 1981 int (*set_reg)(struct radeon_device *rdev, int reg, member
2829 #define radeon_set_surface_reg(rdev, r, f, p, o, s) ((rdev)->asic->surface.set_reg((rdev), (r), (f)…
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| /netbsd-src/sys/arch/arm/nvidia/ |
| H A D | tegra124_car.c | 349 .set_reg = (_set), \
672 u_int set_reg; member
678 u_int set_reg; member
1372 if (tgate->set_reg == tgate->clr_reg) { in tegra124_car_clock_enable_gate()
1373 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); in tegra124_car_clock_enable_gate()
1379 bus_space_write_4(bst, bsh, tgate->set_reg, v); in tegra124_car_clock_enable_gate()
1382 reg = tgate->set_reg; in tegra124_car_clock_enable_gate()
1545 rst->set_reg = tegra124_car_reset_regs[reg].set_reg; in tegra124_car_reset_acquire()
1566 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); in tegra124_car_reset_assert()
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| H A D | tegra210_car.c | 361 .set_reg = (_set), \
686 u_int set_reg; member
692 u_int set_reg; member
1470 if (tgate->set_reg == tgate->clr_reg) { in tegra210_car_clock_enable_gate()
1471 uint32_t v = bus_space_read_4(bst, bsh, tgate->set_reg); in tegra210_car_clock_enable_gate()
1477 bus_space_write_4(bst, bsh, tgate->set_reg, v); in tegra210_car_clock_enable_gate()
1480 reg = tgate->set_reg; in tegra210_car_clock_enable_gate()
1635 rst->set_reg = tegra210_car_reset_regs[reg].set_reg; in tegra210_car_reset_acquire()
1656 bus_space_write_4(sc->sc_bst, sc->sc_bsh, rst->set_reg, rst->mask); in tegra210_car_reset_assert()
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| H A D | tegra_clock.h | 69 u_int set_reg; member
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| /netbsd-src/external/gpl3/gcc.old/dist/libgcc/config/ia64/ |
| H A D | unwind-ia64.c | 463 set_reg (struct unw_reg_info *reg, enum unw_where where, in set_reg() function
608 set_reg (sr->curr.reg + save_order[i], UNW_WHERE_GR, in desc_prologue()
640 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_GR, in desc_br_gr()
655 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_SPILL_HOME, in desc_br_mem()
673 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
684 set_reg (sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
701 set_reg (sr->curr.reg + UNW_REG_F2 + i, UNW_WHERE_SPILL_HOME, in desc_fr_mem()
718 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_GR, in desc_gr_gr()
733 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_gr_mem()
744 set_reg (sr->curr.reg + UNW_REG_PSP, UNW_WHERE_NONE, in desc_mem_stack_f()
[all …]
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| /netbsd-src/external/gpl3/gcc/dist/libgcc/config/ia64/ |
| H A D | unwind-ia64.c | 463 set_reg (struct unw_reg_info *reg, enum unw_where where, in set_reg() function
608 set_reg (sr->curr.reg + save_order[i], UNW_WHERE_GR, in desc_prologue()
640 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_GR, in desc_br_gr()
655 set_reg (sr->curr.reg + UNW_REG_B1 + i, UNW_WHERE_SPILL_HOME, in desc_br_mem()
673 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
684 set_reg (sr->curr.reg + base + i, UNW_WHERE_SPILL_HOME, in desc_frgr_mem()
701 set_reg (sr->curr.reg + UNW_REG_F2 + i, UNW_WHERE_SPILL_HOME, in desc_fr_mem()
718 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_GR, in desc_gr_gr()
733 set_reg (sr->curr.reg + UNW_REG_R4 + i, UNW_WHERE_SPILL_HOME, in desc_gr_mem()
744 set_reg (sr->curr.reg + UNW_REG_PSP, UNW_WHERE_NONE, in desc_mem_stack_f()
[all …]
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/iq2000/ |
| H A D | iq2000.cc | 390 rtx set_reg; in iq2000_fill_delay_slot() local
414 || (set_reg = operands[0]) == 0) in iq2000_fill_delay_slot()
425 set_reg = operands[0]; in iq2000_fill_delay_slot()
426 if (set_reg == 0) in iq2000_fill_delay_slot()
429 while (GET_CODE (set_reg) == SUBREG) in iq2000_fill_delay_slot()
430 set_reg = SUBREG_REG (set_reg); in iq2000_fill_delay_slot()
432 mode = GET_MODE (set_reg); in iq2000_fill_delay_slot()
434 iq2000_load_reg = set_reg; in iq2000_fill_delay_slot()
437 iq2000_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1); in iq2000_fill_delay_slot()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/iq2000/ |
| H A D | iq2000.c | 390 rtx set_reg; in iq2000_fill_delay_slot() local
414 || (set_reg = operands[0]) == 0) in iq2000_fill_delay_slot()
425 set_reg = operands[0]; in iq2000_fill_delay_slot()
426 if (set_reg == 0) in iq2000_fill_delay_slot()
429 while (GET_CODE (set_reg) == SUBREG) in iq2000_fill_delay_slot()
430 set_reg = SUBREG_REG (set_reg); in iq2000_fill_delay_slot()
432 mode = GET_MODE (set_reg); in iq2000_fill_delay_slot()
434 iq2000_load_reg = set_reg; in iq2000_fill_delay_slot()
437 iq2000_load_reg2 = gen_rtx_REG (SImode, REGNO (set_reg) + 1); in iq2000_fill_delay_slot()
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/ |
| H A D | web.c | 84 void set_reg (rtx r) { reg_pvt = r; } in set_reg() function
280 root->set_reg (newreg); in entry_register()
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| /netbsd-src/external/gpl3/gcc/dist/gcc/ |
| H A D | web.cc | 84 void set_reg (rtx r) { reg_pvt = r; } in set_reg() function
280 root->set_reg (newreg); in entry_register()
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| /netbsd-src/external/gpl3/gcc/dist/gcc/config/nds32/ |
| H A D | nds32-intrinsic.md | 386 rtx set_reg = gen_reg_rtx (SImode);
430 emit_move_insn (set_reg, priority);
433 emit_insn (gen_iorsi3 (temp_reg, temp_reg, set_reg));
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| /netbsd-src/external/gpl3/gcc.old/dist/gcc/config/nds32/ |
| H A D | nds32-intrinsic.md | 386 rtx set_reg = gen_reg_rtx (SImode);
430 emit_move_insn (set_reg, priority);
433 emit_insn (gen_iorsi3 (temp_reg, temp_reg, set_reg));
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| /netbsd-src/external/gpl3/gcc/dist/libgcc/ |
| H A D | ChangeLog | 8541 (set_reg, alloc_spill_area, finish_prologue, ia64_rse_slot_num)
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