| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | MachineRegisterInfo.cpp | 58 MachineRegisterInfo::setRegClass(Register Reg, const TargetRegisterClass *RC) { in setRegClass() function in MachineRegisterInfo
80 MRI.setRegClass(Reg, NewRC); in constrainRegClass()
142 setRegClass(Reg, NewRC); in recomputeRegClass()
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| H A D | TailDuplicator.cpp | 422 MRI->setRegClass(VI->second.Reg, ConstrRC); in duplicateInstruction()
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| H A D | MachineLICM.cpp | 1348 MRI->setRegClass(Dup->getOperand(Defs[j]).getReg(), OrigRCs[j]); in EliminateCSE()
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| H A D | RegisterCoalescer.cpp | 1414 MRI->setRegClass(DstReg, NewRC); in reMaterializeTrivialDef()
2051 MRI->setRegClass(CP.getDstReg(), CP.getNewRC()); in joinCopy()
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| H A D | ModuloSchedule.cpp | 1902 MRI.setRegClass(R, MRI.getRegClass(PhiR)); in rewriteUsesOf()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIFixSGPRCopies.cpp | 199 MRI.setRegClass(DstReg, TRI->getEquivalentSGPRClass(MRI.getRegClass(DstReg))); in tryChangeVGPRtoSGPRinCopy()
251 MRI.setRegClass(DstReg, DstRC); in foldVGPRCopyIntoRegSequence()
825 MRI->setRegClass(PHIRes, TRI->getEquivalentAGPRClass(RC0)); in processPHINode()
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| H A D | SILowerI1Copies.cpp | 565 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerPhis()
686 MRI->setRegClass(DstReg, IsWave32 ? &AMDGPU::SReg_32RegClass in lowerCopiesToI1()
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| H A D | SIFoldOperands.cpp | 1686 MRI->setRegClass(DefReg, TRI->getEquivalentAGPRClass(RC)); in tryFoldLoad()
1688 MRI->setRegClass(DefReg, RC); in tryFoldLoad()
1694 MRI->setRegClass(Reg, TRI->getEquivalentAGPRClass(MRI->getRegClass(Reg))); in tryFoldLoad()
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| H A D | AMDGPUInstructionSelector.cpp | 167 MRI->setRegClass(SrcReg, SrcRC); in selectCOPY()
441 MRI->setRegClass(Dst1Reg, &AMDGPU::SReg_32RegClass); in selectG_UADDO_USUBO_UADDE_USUBE()
921 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectG_INTRINSIC()
1231 MRI->setRegClass(Reg, TRI.getWaveMaskRegClass()); in selectEndCfIntrinsic()
1783 MRI->setRegClass(CCReg, TRI.getConstrainedRegClassForOperand(CCOp, *MRI)); in selectG_SELECT()
2422 MRI->setRegClass( in selectG_AMDGPU_ATOMIC_CMPXCHG()
2461 MRI->setRegClass(CondReg, ConstrainRC); in selectG_BRCOND()
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| H A D | AMDGPURegisterBankInfo.cpp | 918 MRI.setRegClass(UnmergePiece, &AMDGPU::VReg_64RegClass); in executeInWaterfallLoop()
919 MRI.setRegClass(CurrentLaneOpRegLo, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
920 MRI.setRegClass(CurrentLaneOpRegHi, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
937 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_64_XEXECRegClass); in executeInWaterfallLoop()
950 MRI.setRegClass(UnmergePiece, &AMDGPU::VGPR_32RegClass); in executeInWaterfallLoop()
951 MRI.setRegClass(CurrentLaneOpReg, &AMDGPU::SReg_32_XM0RegClass); in executeInWaterfallLoop()
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| H A D | AMDGPULegalizerInfo.cpp | 2270 B.getMRI()->setRegClass(PCReg, &AMDGPU::SReg_64RegClass); in buildPCRelGlobalAddress()
4728 MRI.setRegClass(Def, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
4729 MRI.setRegClass(Use, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
4764 MRI.setRegClass(Reg, TRI->getWaveMaskRegClass()); in legalizeIntrinsic()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 412 MRI.setRegClass(Addr.Base.Reg, &PPC::G8RC_and_G8RC_NOX0RegClass); in PPCComputeAddress()
1313 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1317 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
1330 MRI.setRegClass(SrcReg1, &PPC::GPRC_and_GPRC_NOR0RegClass); in SelectBinaryIntOp()
1339 MRI.setRegClass(SrcReg1, &PPC::G8RC_and_G8RC_NOX0RegClass); in SelectBinaryIntOp()
2429 MRI.setRegClass(Op0, &PPC::GPRC_and_GPRC_NOR0RegClass); in fastEmitInst_ri()
2431 MRI.setRegClass(Op0, &PPC::G8RC_and_G8RC_NOX0RegClass); in fastEmitInst_ri()
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| H A D | PPCMIPeephole.cpp | 946 MRI->setRegClass(DominatorReg, TRC); in simplifyCode()
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| H A D | PPCInstrInfo.cpp | 5036 MRI.setRegClass(RegToModify, NewRC); in transformToImmFormFedByLI()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InstructionSelect.cpp | 178 MRI.setRegClass(SrcReg, DstRC); in runOnMachineFunction()
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| H A D | RegisterBankInfo.cpp | 146 MRI.setRegClass(Reg, &RC); in constrainGenericRegister()
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| H A D | IRTranslator.cpp | 1616 MRI->setRegClass(DstReg, TRI->getPointerRegClass(*MF)); in getStackGuard()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64LegalizerInfo.cpp | 872 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
894 MRI.setRegClass(ADRP.getReg(0), &AArch64::GPR64RegClass); in legalizeSmallCMGlobalValue()
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| H A D | AArch64InstructionSelector.cpp | 1908 MRI.setRegClass(NewSrc.getReg(0), &AArch64::GPR64RegClass); in preISelLower()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.cpp | 1310 MRI.setRegClass(Reg, &SystemZ::FP32BitRegClass); in foldMemoryOperandImpl()
1312 MRI.setRegClass(Reg, &SystemZ::FP64BitRegClass); in foldMemoryOperandImpl()
1314 MRI.setRegClass(Reg, &SystemZ::VF128BitRegClass); in foldMemoryOperandImpl()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86DomainReassignment.cpp | 507 MRI->setRegClass(Reg, getDstRC(MRI->getRegClass(Reg), Domain)); in reassign()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | MachineRegisterInfo.h | 673 void setRegClass(Register Reg, const TargetRegisterClass *RC);
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsInstructionSelector.cpp | 580 MRI.setRegClass(Dst, getRegClassForTypeOnBank(Dst, MRI)); in select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/MIRParser/ |
| H A D | MIRParser.cpp | 638 MRI.setRegClass(Reg, Info.D.RC); in setupRegisterInfo()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | InstrEmitter.cpp | 658 MRI->setRegClass(NewVReg, SRC); in EmitRegSequence()
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