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Searched refs:setReg (Results 1 – 25 of 147) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DMachineLoopUtils.cpp56 MO.setReg(R); in PeelSingleBlockLoop()
68 Use->setReg(R); in PeelSingleBlockLoop()
77 MO.setReg(Remaps[MO.getReg()]); in PeelSingleBlockLoop()
92 OrigPhi.getOperand(InitRegIdx).setReg(R); in PeelSingleBlockLoop()
99 MI.getOperand(LoopRegIdx).setReg(LoopReg); in PeelSingleBlockLoop()
H A DBreakFalseDeps.cpp145 MO.setReg(CurrMO.getReg()); in pickBestRegisterForUndef()
167 MO.setReg(MaxClearanceReg); in pickBestRegisterForUndef()
H A DModuloSchedule.cpp343 O.setReg(ToReg); in replaceRegUsesAfterLoop()
1039 MO.setReg(NewReg); in updateInstruction()
1055 MO.setReg(VRMap[StageNum][reg]); in updateInstruction()
1189 UseOp.setReg(ReplaceReg); in rewriteScheduledInstr()
1328 MO.setReg(Reg); in rewrite()
1482 MI->getOperand(1).setReg(InitReg.getValue()); in phi()
1665 MI.getOperand(0).setReg(PhiReg); in moveStageBetweenBlocks()
1679 NewMI->getOperand(0).setReg(R); in moveStageBetweenBlocks()
1680 NewMI->getOperand(1).setReg(OrigR); in moveStageBetweenBlocks()
1693 MO.setReg(Remaps[MO.getReg()]); in moveStageBetweenBlocks()
[all …]
H A DTailDuplicator.cpp402 MO.setReg(NewReg); in duplicateInstruction()
433 MO.setReg(VI->second.Reg); in duplicateInstruction()
451 MO.setReg(NewReg); in duplicateInstruction()
522 MI.getOperand(Idx).setReg(SrcReg); in updateSuccessorsPHIs()
534 MI.getOperand(Idx).setReg(Reg); in updateSuccessorsPHIs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCVSXFMAMutate.cpp246 MI.getOperand(0).setReg(KilledProdReg); in processBlock()
247 MI.getOperand(1).setReg(KilledProdReg); in processBlock()
248 MI.getOperand(3).setReg(AddendSrcReg); in processBlock()
265 MI.getOperand(2).setReg(AddendSrcReg); in processBlock()
270 MI.getOperand(2).setReg(OtherProdReg); in processBlock()
H A DPPCMIPeephole.cpp589 MI.getOperand(1).setReg(DefReg1); in simplifyCode()
590 MI.getOperand(2).setReg(DefReg2); in simplifyCode()
611 DefMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
679 MI.getOperand(1).setReg(ShiftOp1); in simplifyCode()
723 Use.getOperand(i).setReg(ConvReg1); in simplifyCode()
783 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
827 SrcMI->getOperand(0).setReg(MI.getOperand(0).getReg()); in simplifyCode()
1465 CMPI2->getOperand(1).setReg(Op2); in eliminateRedundantCompare()
1466 CMPI2->getOperand(2).setReg(Op1); in eliminateRedundantCompare()
1480 CMPI2->getOperand(I).setReg(SrcReg); in eliminateRedundantCompare()
[all …]
H A DPPCVSXCopy.cpp114 SrcMO.setReg(NewVReg); in processBlock()
133 SrcMO.setReg(NewVReg); in processBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyDebugValueManager.cpp67 MO.setReg(Reg); in updateReg()
78 MO.setReg(NewReg); in clone()
H A DWebAssemblyFixBrTableDefaults.cpp65 MI.getOperand(0).setReg(ExtMI->getOperand(1).getReg()); in fixBrTableIndex()
74 MI.getOperand(0).setReg(Reg32); in fixBrTableIndex()
H A DWebAssemblyPeephole.cpp67 MO.setReg(NewReg); in maybeRewriteToDrop()
126 MO.setReg(NewReg); in maybeRewriteToFallthrough()
H A DWebAssemblyExplicitLocals.cpp282 MI.getOperand(2).setReg(NewReg); in runOnMachineFunction()
331 Def.setReg(NewReg); in runOnMachineFunction()
384 MO.setReg(NewReg); in runOnMachineFunction()
H A DWebAssemblyRegStackify.cpp533 Def->getOperand(0).setReg(NewReg); in moveForSingleUse()
534 Op.setReg(NewReg); in moveForSingleUse()
570 Op.setReg(NewReg); in rematerializeCheapDef()
647 Op.setReg(TeeReg); in moveAndTeeForMultiUse()
648 DefMO.setReg(DefReg); in moveAndTeeForMultiUse()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonAsmPrinter.cpp381 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
392 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
404 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
416 Rs.setReg(getHexagonRegisterPair(Rs.getReg(), RI)); in HexagonProcessInstruction()
542 MO.setReg(High); in HexagonProcessInstruction()
554 MO.setReg(High); in HexagonProcessInstruction()
568 MO.setReg(High); in HexagonProcessInstruction()
601 Rt.setReg(getHexagonRegisterPair(Rt.getReg(), RI)); in HexagonProcessInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZCopyPhysRegs.cpp95 MI->getOperand(1).setReg(Tmp); in visitMBB()
101 MI->getOperand(0).setReg(Tmp); in visitMBB()
H A DSystemZPostRewrite.cpp125 MBBI->getOperand(1).setReg(DestReg); in selectSELRMux()
132 MBBI->getOperand(2).setReg(DestReg); in selectSELRMux()
230 SrcMO.setReg(DstReg); in selectMI()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp392 LoopPhi->getOperand(3).setReg(StartReg); in MergeLoopEnd()
393 LoopPhi->getOperand(1).setReg(DecReg); in MergeLoopEnd()
395 LoopPhi->getOperand(1).setReg(StartReg); in MergeLoopEnd()
396 LoopPhi->getOperand(3).setReg(DecReg); in MergeLoopEnd()
603 User.setReg(NewResult); in ReplaceRegisterUseWithVPNOT()
769 MO->setReg(LastVPNOTResult); in ReduceOldVCCRValueUses()
923 Instr.getOperand(PIdx + 1).setReg(LastVPTReg); in ReplaceConstByVPNOTs()
940 Instr.getOperand(PIdx + 1).setReg(NewVPR); in ReplaceConstByVPNOTs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DDelaySlotFiller.cpp396 AddMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreADD()
435 OrMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreOR()
469 RestoreMI->getOperand(0).setReg(reg - SP::I0 + SP::O0); in combineRestoreSETHIi()
470 RestoreMI->getOperand(1).setReg(SP::G0); in combineRestoreSETHIi()
H A DSparcRegisterInfo.cpp193 MI.getOperand(2).setReg(SrcOddReg); in eliminateFrameIndex()
206 MI.getOperand(0).setReg(DestOddReg); in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/AsmParser/
H A DHexagonAsmParser.cpp1411 MO.setReg(RegPair.first); in processInstruction()
1421 MO.setReg(RegPair.first); in processInstruction()
1432 MO.setReg(RegPair.first); in processInstruction()
1444 MO.setReg(RegPair.first); in processInstruction()
1758 Rss.setReg(matchRegister(Reg1)); in processInstruction()
1784 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1789 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1801 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1806 Rs.setReg(matchRegister(RegPair)); in processInstruction()
1818 Rt.setReg(matchRegister(RegPair)); in processInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64PreLegalizerCombiner.cpp105 MI.getOperand(2).setReg(WideReg); in applyICmpRedundantTrunc()
106 MI.getOperand(3).setReg(WideZero.getReg(0)); in applyICmpRedundantTrunc()
215 MI.getOperand(0).setReg(NewGVDst); in applyFoldGlobalOffset()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrBuilder.h137 MI->getOperand(Operand + 2).setReg(0); in setDirectAddressInInstr()
139 MI->getOperand(Operand + 4).setReg(0); in setDirectAddressInInstr()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DLocalizer.cpp136 LocalizedMI->getOperand(0).setReg(NewReg); in localizeInterBlock()
144 MOUse.setReg(NewVRegIt->second); in localizeInterBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVERegisterInfo.cpp176 MI.getOperand(3).setReg(SrcHiReg); in eliminateFrameIndex()
191 MI.getOperand(0).setReg(DestHiReg); in eliminateFrameIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsOptimizePICCall.cpp158 I->getOperand(0).setReg(DstReg); in setCallTargetReg()
248 getCallTargetRegOpnd(*I)->setReg(getReg(Entry)); in visitNode()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.cpp932 MO2.setReg(R600::PRED_SEL_ONE); in reverseBranchCondition()
935 MO2.setReg(R600::PRED_SEL_ZERO); in reverseBranchCondition()
960 .setReg(Pred[2].getReg()); in PredicateInstruction()
962 .setReg(Pred[2].getReg()); in PredicateInstruction()
964 .setReg(Pred[2].getReg()); in PredicateInstruction()
966 .setReg(Pred[2].getReg()); in PredicateInstruction()
974 PMO.setReg(Pred[2].getReg()); in PredicateInstruction()
1330 .setReg(MO.getReg()); in buildSlotOfVectorInstruction()

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