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Searched refs:scl_data (Results 1 – 19 of 19) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_dpp_dscl.c303 const struct scaler_data *scl_data, in dpp1_dscl_set_scl_filter() argument
310 uint32_t h_2tap_sharp_factor = scl_data->sharpness.horz; in dpp1_dscl_set_scl_filter()
311 uint32_t v_2tap_sharp_factor = scl_data->sharpness.vert; in dpp1_dscl_set_scl_filter()
318 h_2tap_hardcode_coef_en = scl_data->taps.h_taps < 3 in dpp1_dscl_set_scl_filter()
319 && scl_data->taps.h_taps_c < 3 in dpp1_dscl_set_scl_filter()
320 && (scl_data->taps.h_taps > 1 && scl_data->taps.h_taps_c > 1); in dpp1_dscl_set_scl_filter()
321 v_2tap_hardcode_coef_en = scl_data->taps.v_taps < 3 in dpp1_dscl_set_scl_filter()
322 && scl_data->taps.v_taps_c < 3 in dpp1_dscl_set_scl_filter()
323 && (scl_data->taps.v_taps > 1 && scl_data->taps.v_taps_c > 1); in dpp1_dscl_set_scl_filter()
340 scl_data->taps.h_taps, scl_data->ratios.horz); in dpp1_dscl_set_scl_filter()
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H A Damdgpu_dcn10_dpp.c139 struct scaler_data *scl_data, in dpp1_get_optimal_number_of_taps() argument
144 if (scl_data->viewport.width > scl_data->recout.width) in dpp1_get_optimal_number_of_taps()
145 pixel_width = scl_data->recout.width; in dpp1_get_optimal_number_of_taps()
147 pixel_width = scl_data->viewport.width; in dpp1_get_optimal_number_of_taps()
150 if (scl_data->format == PIXEL_FORMAT_FP16 && in dpp1_get_optimal_number_of_taps()
152 scl_data->ratios.horz.value != dc_fixpt_one.value && in dpp1_get_optimal_number_of_taps()
153 scl_data->ratios.vert.value != dc_fixpt_one.value) in dpp1_get_optimal_number_of_taps()
156 if (scl_data->viewport.width > scl_data->h_active && in dpp1_get_optimal_number_of_taps()
158 scl_data->viewport.width > dpp->ctx->dc->debug.max_downscale_src_width) in dpp1_get_optimal_number_of_taps()
164 if (scl_data->ratios.horz.value == (4ll << 32)) in dpp1_get_optimal_number_of_taps()
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H A Damdgpu_dcn10_hw_sequencer.c2051 switch (pipe_ctx->plane_res.scl_data.format) { in dcn10_get_surface_visual_confirm_color()
2093 switch (top_pipe_ctx->plane_res.scl_data.format) { in dcn10_get_hdr_visual_confirm_color()
2226 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = per_pixel_alpha; in update_scaler()
2227 pipe_ctx->plane_res.scl_data.lb_params.depth = LB_PIXEL_DEPTH_30BPP; in update_scaler()
2230 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in update_scaler()
2288 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; in dcn10_update_dchubp_dpp()
2312 &pipe_ctx->plane_res.scl_data.viewport, in dcn10_update_dchubp_dpp()
2313 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn10_update_dchubp_dpp()
2922 const struct rect *r1 = &pipe_ctx->plane_res.scl_data.recout, *r2; in dcn10_can_pipe_disable_cursor()
2935 r2 = &test_pipe->plane_res.scl_data.recout; in dcn10_can_pipe_disable_cursor()
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H A Ddcn10_dpp.h1361 struct scaler_data scl_data; member
1392 const struct scaler_data *scl_data,
1484 const struct scaler_data *scl_data);
1507 struct scaler_data *scl_data,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_dpp.c270 const struct scaler_data *scl_data, in dscl2_calc_lb_num_partitions() argument
278 int line_size = scl_data->viewport.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
279 scl_data->viewport.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
280 int line_size_c = scl_data->viewport_c.width < scl_data->recout.width ? in dscl2_calc_lb_num_partitions()
281 scl_data->viewport_c.width : scl_data->recout.width; in dscl2_calc_lb_num_partitions()
315 if (scl_data->lb_params.alpha_en in dscl2_calc_lb_num_partitions()
381 struct scaler_data *scl_data, in dpp2_get_optimal_number_of_taps() argument
385 if (scl_data->viewport.width != scl_data->h_active && in dpp2_get_optimal_number_of_taps()
386 scl_data->viewport.height != scl_data->v_active && in dpp2_get_optimal_number_of_taps()
388 scl_data->format == PIXEL_FORMAT_FP16) in dpp2_get_optimal_number_of_taps()
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H A Damdgpu_dcn20_hwseq.c1248 …if (memcmp(&old_pipe->plane_res.scl_data, &new_pipe->plane_res.scl_data, sizeof(struct scaler_data… in dcn20_detect_pipe_changes()
1251 …if (memcmp(&old_pipe->plane_res.scl_data.viewport, &new_pipe->plane_res.scl_data.viewport, sizeof(… in dcn20_detect_pipe_changes()
1252 || memcmp(&old_pipe->plane_res.scl_data.viewport_c, in dcn20_detect_pipe_changes()
1253 &new_pipe->plane_res.scl_data.viewport_c, sizeof(struct rect))) in dcn20_detect_pipe_changes()
1389 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->plane_state->per_pixel_alpha; in dcn20_update_dchubp_dpp()
1390 ASSERT(pipe_ctx->plane_res.scl_data.lb_params.depth == LB_PIXEL_DEPTH_30BPP); in dcn20_update_dchubp_dpp()
1393 pipe_ctx->plane_res.dpp, &pipe_ctx->plane_res.scl_data); in dcn20_update_dchubp_dpp()
1402 &pipe_ctx->plane_res.scl_data.viewport, in dcn20_update_dchubp_dpp()
1403 &pipe_ctx->plane_res.scl_data.viewport_c); in dcn20_update_dchubp_dpp()
1446 size.surface_size = pipe_ctx->plane_res.scl_data.viewport; in dcn20_update_dchubp_dpp()
H A Damdgpu_dcn20_resource.c1753 struct scaler_data *sd = &prev_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
1770 sd = &next_odm_pipe->plane_res.scl_data; in dcn20_split_stream_for_odm()
2101 struct scaler_data *scl = &res_ctx->pipe_ctx[i].plane_res.scl_data; in dcn20_populate_dml_pipes_from_context()
2136 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
2138 res_ctx->pipe_ctx[i].bottom_pipe->plane_res.scl_data.recout.height; in dcn20_populate_dml_pipes_from_context()
2141 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.width; in dcn20_populate_dml_pipes_from_context()
2143 res_ctx->pipe_ctx[i].top_pipe->plane_res.scl_data.recout.height; in dcn20_populate_dml_pipes_from_context()
H A Ddcn20_dpp.h697 struct scaler_data scl_data; member
750 const struct scaler_data *scl_data,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_resource.c544 struct scaler_data *data = &pipe_ctx->plane_res.scl_data; in calculate_viewport()
659 pipe_ctx->plane_res.scl_data.recout.x = stream->dst.x; in calculate_recout()
661 pipe_ctx->plane_res.scl_data.recout.x += (surf_clip.x in calculate_recout()
665 pipe_ctx->plane_res.scl_data.recout.width = surf_clip.width * in calculate_recout()
667 if (pipe_ctx->plane_res.scl_data.recout.width + pipe_ctx->plane_res.scl_data.recout.x > in calculate_recout()
669 pipe_ctx->plane_res.scl_data.recout.width = in calculate_recout()
671 - pipe_ctx->plane_res.scl_data.recout.x; in calculate_recout()
673 pipe_ctx->plane_res.scl_data.recout.y = stream->dst.y; in calculate_recout()
675 pipe_ctx->plane_res.scl_data.recout.y += (surf_clip.y in calculate_recout()
679 pipe_ctx->plane_res.scl_data.recout.height = surf_clip.height * in calculate_recout()
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H A Damdgpu_dc.c470 pipes->plane_res.scl_data.lb_params.depth, in dc_stream_set_dither_option()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_transform.c898 struct scaler_data *scl_data, in dce_transform_get_optimal_number_of_taps() argument
902 int pixel_width = scl_data->viewport.width; in dce_transform_get_optimal_number_of_taps()
906 (scl_data->viewport.width > scl_data->recout.width)) in dce_transform_get_optimal_number_of_taps()
907 pixel_width = scl_data->recout.width; in dce_transform_get_optimal_number_of_taps()
911 scl_data->lb_params.depth, in dce_transform_get_optimal_number_of_taps()
927 scl_data->taps.h_taps = decide_taps(scl_data->ratios.horz, in_taps->h_taps, false); in dce_transform_get_optimal_number_of_taps()
928 scl_data->taps.v_taps = decide_taps(scl_data->ratios.vert, in_taps->v_taps, false); in dce_transform_get_optimal_number_of_taps()
929 scl_data->taps.h_taps_c = decide_taps(scl_data->ratios.horz_c, in_taps->h_taps, true); in dce_transform_get_optimal_number_of_taps()
930 scl_data->taps.v_taps_c = decide_taps(scl_data->ratios.vert_c, in_taps->v_taps, true); in dce_transform_get_optimal_number_of_taps()
932 if (!IDENTITY_RATIO(scl_data->ratios.vert)) { in dce_transform_get_optimal_number_of_taps()
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H A Ddce_transform.h496 struct scaler_data *scl_data,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
H A Damdgpu_dcn_calcs.c338 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
339 input->src.viewport_height = pipe->plane_res.scl_data.viewport.height; in pipe_ctx_to_e2e_pipe_params()
340 input->src.data_pitch = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
341 input->src.data_pitch_c = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
389 input->scale_taps.htaps = pipe->plane_res.scl_data.taps.h_taps; in pipe_ctx_to_e2e_pipe_params()
390 input->scale_ratio_depth.hscl_ratio = pipe->plane_res.scl_data.ratios.horz.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
391 input->scale_ratio_depth.vscl_ratio = pipe->plane_res.scl_data.ratios.vert.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
392 input->scale_ratio_depth.vinit = pipe->plane_res.scl_data.inits.v.value/4294967296.0; in pipe_ctx_to_e2e_pipe_params()
395 input->scale_taps.vtaps = pipe->plane_res.scl_data.taps.v_taps; in pipe_ctx_to_e2e_pipe_params()
396 input->scale_taps.vtaps_c = pipe->plane_res.scl_data.taps.v_taps_c; in pipe_ctx_to_e2e_pipe_params()
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H A Damdgpu_dce_calcs.c2804 data->src_width[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.width); in populate_initial_data()
2806 data->src_height[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.viewport.height); in populate_initial_data()
2807 data->h_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.h_taps); in populate_initial_data()
2808 data->v_taps[num_displays + 4] = bw_int_to_fixed(pipe[i].plane_res.scl_data.taps.v_taps); in populate_initial_data()
2809 …data->h_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.h… in populate_initial_data()
2810 …data->v_scale_ratio[num_displays + 4] = fixed31_32_to_bw_fixed(pipe[i].plane_res.scl_data.ratios.v… in populate_initial_data()
2858 …data->src_height[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.v… in populate_initial_data()
2859 …data->src_width[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.vi… in populate_initial_data()
2862 …data->h_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
2863 …data->v_taps[num_displays * 2 + j] = bw_int_to_fixed(pipe[i].bottom_pipe->plane_res.scl_data.taps.… in populate_initial_data()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_transform_v.c55 const struct scaler_data *scl_data, in calculate_viewport() argument
60 luma_viewport->x = scl_data->viewport.x - scl_data->viewport.x % 2; in calculate_viewport()
61 luma_viewport->y = scl_data->viewport.y - scl_data->viewport.y % 2; in calculate_viewport()
63 scl_data->viewport.width - scl_data->viewport.width % 2; in calculate_viewport()
65 scl_data->viewport.height - scl_data->viewport.height % 2; in calculate_viewport()
71 if (scl_data->format == PIXEL_FORMAT_420BPP8) { in calculate_viewport()
H A Damdgpu_dce110_hw_sequencer.c1199 switch (pipe_ctx->plane_res.scl_data.format) { in get_surface_visual_confirm_color()
1249 pipe_ctx->plane_res.scl_data.lb_params.depth, in program_scaler()
1267 &pipe_ctx->plane_res.scl_data); in program_scaler()
1421 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in apply_single_controller_ctx_to_hw()
2114 default_adjust.surface_pixel_format = pipe_ctx->plane_res.scl_data.format; in set_default_colors()
2121 default_adjust.lb_color_depth = pipe_ctx->plane_res.scl_data.lb_params.depth; in set_default_colors()
2499 pipe_ctx->plane_res.scl_data.lb_params.alpha_en = pipe_ctx->bottom_pipe != 0; in dce110_program_front_end_for_pipe()
2558 pipe_ctx->plane_res.scl_data.viewport.width, in dce110_program_front_end_for_pipe()
2559 pipe_ctx->plane_res.scl_data.viewport.height, in dce110_program_front_end_for_pipe()
2560 pipe_ctx->plane_res.scl_data.viewport.x, in dce110_program_front_end_for_pipe()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/hw/
H A Dtransform.h190 const struct scaler_data *scl_data);
199 struct scaler_data *scl_data,
301 const struct scaler_data *scl_data,
H A Ddpp.h139 const struct scaler_data *scl_data);
148 struct scaler_data *scl_data,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/inc/
H A Dcore_types.h248 struct scaler_data scl_data; member