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Searched refs:regclasses (Results 1 – 10 of 10) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp63 for (const TargetRegisterClass *RC : TRI->regclasses()) in ResourcePriorityQueue()
364 for (const TargetRegisterClass *RC : TRI->regclasses()) in regPressureDelta()
368 for (const TargetRegisterClass *RC : TRI->regclasses()) { in regPressureDelta()
H A DScheduleDAGRRList.cpp1767 for (const TargetRegisterClass *RC : TRI->regclasses()) in RegReductionPQBase()
2076 for (const TargetRegisterClass *RC : TRI->regclasses()) { in dumpRegPressure()
H A DTargetLowering.cpp4577 for (const TargetRegisterClass *RC : RI->regclasses()) { in getRegForInlineAsmConstraint()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetRegisterInfo.cpp218 for (const TargetRegisterClass* RC : regclasses()) { in getMinimalPhysRegClass()
236 for (const TargetRegisterClass *RC : regclasses()) { in getMinimalPhysRegClassLLT()
264 for (const TargetRegisterClass *C : regclasses()) in getAllocatableSet()
H A DRegisterClassInfo.cpp174 for (const TargetRegisterClass *C : TRI->regclasses()) { in computePSetLimit()
H A DRDFRegisters.cpp33 for (const TargetRegisterClass *RC : TRI.regclasses()) { in PhysicalRegisterInfo()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/
H A DMCRegisterInfo.h533 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h727 iterator_range<regclass_iterator> regclasses() const { in regclasses() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonBlockRanges.cpp224 for (const TargetRegisterClass *RC : TRI.regclasses()) { in HexagonBlockRanges()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedFalkorDetails.td581 // FIXME: This could be better modeled by looking at the regclasses of the operands.