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Searched refs:reg_num (Results 1 – 25 of 54) sorted by relevance

123

/netbsd-src/sys/dev/pci/
H A Dunichromehw.h255 int reg_num; member
261 int reg_num; member
267 int reg_num; member
273 int reg_num; member
279 int reg_num; member
285 int reg_num; member
291 int reg_num; member
297 int reg_num; member
303 int reg_num; member
309 int reg_num; member
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H A Dunichromefb.c825 regnum = iga1_crtc_reg.hor_total.reg_num; in uni_load_crtc()
831 regnum = iga1_crtc_reg.hor_addr.reg_num; in uni_load_crtc()
837 regnum = iga1_crtc_reg.hor_blank_start.reg_num; in uni_load_crtc()
844 regnum = iga1_crtc_reg.hor_blank_end.reg_num; in uni_load_crtc()
850 regnum = iga1_crtc_reg.hor_sync_start.reg_num; in uni_load_crtc()
857 regnum = iga1_crtc_reg.hor_sync_end.reg_num; in uni_load_crtc()
863 regnum = iga1_crtc_reg.ver_total.reg_num; in uni_load_crtc()
869 regnum = iga1_crtc_reg.ver_addr.reg_num; in uni_load_crtc()
875 regnum = iga1_crtc_reg.ver_blank_start.reg_num; in uni_load_crtc()
882 regnum = iga1_crtc_reg.ver_blank_end.reg_num; in uni_load_crtc()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce120/
H A Damdgpu_irq_service_dce120.c110 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
111 .enable_reg = SRI(reg1, block, reg_num),\
113 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
115 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
116 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
118 .ack_reg = SRI(reg2, block, reg_num),\
120 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
122 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
124 #define hpd_int_entry(reg_num)\ argument
125 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce80/
H A Damdgpu_irq_service_dce80.c99 #define hpd_int_entry(reg_num)\ argument
100 [DC_IRQ_SOURCE_INVALID + reg_num] = {\
101 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
107 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
110 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
114 #define hpd_rx_int_entry(reg_num)\ argument
115 [DC_IRQ_SOURCE_HPD6 + reg_num] = {\
116 .enable_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
121 .ack_reg = mmDC_HPD ## reg_num ## _INT_CONTROL,\
124 .status_reg = mmDC_HPD ## reg_num ## _INT_STATUS,\
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn20/
H A Damdgpu_irq_service_dcn20.c193 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
194 .enable_reg = SRI(reg1, block, reg_num),\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
198 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
199 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
201 .ack_reg = SRI(reg2, block, reg_num),\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
205 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
209 #define hpd_int_entry(reg_num)\ argument
210 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn10/
H A Damdgpu_irq_service_dcn10.c191 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
192 .enable_reg = SRI(reg1, block, reg_num),\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
196 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
197 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
199 .ack_reg = SRI(reg2, block, reg_num),\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
203 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 #define hpd_int_entry(reg_num)\ argument
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dcn21/
H A Damdgpu_irq_service_dcn21.c189 #define IRQ_REG_ENTRY(block, reg_num, reg1, mask1, reg2, mask2)\ argument
190 .enable_reg = SRI(reg1, block, reg_num),\
192 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
194 block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK,\
195 ~block ## reg_num ## _ ## reg1 ## __ ## mask1 ## _MASK \
197 .ack_reg = SRI(reg2, block, reg_num),\
199 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK,\
201 block ## reg_num ## _ ## reg2 ## __ ## mask2 ## _MASK \
205 #define hpd_int_entry(reg_num)\ argument
206 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/irq/dce110/
H A Damdgpu_irq_service_dce110.c96 #define hpd_int_entry(reg_num)\ argument
97 [DC_IRQ_SOURCE_HPD1 + reg_num] = {\
98 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
104 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
107 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
111 #define hpd_rx_int_entry(reg_num)\ argument
112 [DC_IRQ_SOURCE_HPD1RX + reg_num] = {\
113 .enable_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
118 .ack_reg = mmHPD ## reg_num ## _DC_HPD_INT_CONTROL,\
121 .status_reg = mmHPD ## reg_num ## _DC_HPD_INT_STATUS,\
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/netbsd-src/external/gpl3/binutils/dist/gas/config/
H A Dtc-i386-intel.c295 int reg_num; in i386_intel_simplify_register() local
304 reg_num = e->X_add_number; in i386_intel_simplify_register()
306 reg_num = e->X_md - 1; in i386_intel_simplify_register()
308 if (reg_num < 0 || reg_num >= (int) i386_regtab_size) in i386_intel_simplify_register()
314 if (!check_register (&i386_regtab[reg_num])) in i386_intel_simplify_register()
317 register_prefix, i386_regtab[reg_num].reg_name); in i386_intel_simplify_register()
328 if ((i386_regtab[reg_num].reg_type.bitfield.class == SReg in i386_intel_simplify_register()
329 && i386_regtab[reg_num].reg_num == RegFlat) in i386_intel_simplify_register()
331 && i386_regtab[reg_num].reg_type.bitfield.class == ClassNone)) in i386_intel_simplify_register()
336 i.op[this_operand].regs = i386_regtab + reg_num; in i386_intel_simplify_register()
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H A Dtc-i386.c2388 unsigned int nr = r->reg_num; in register_number()
3215 switch (regtab->reg_num) in md_begin()
3224 if (!regtab->reg_num) in md_begin()
4045 register_specifier = i.vex.register_specifier->reg_num; in build_evex_prefix()
4214 i.vex.bytes[3] |= i.mask.reg->reg_num; in build_evex_prefix()
4291 if (i.op[x].regs->reg_num > 3) in establish_rex()
4315 && i.op[x].regs->reg_num > 3) in establish_rex()
4548 if (!i.index_reg && i.base_reg->reg_num != RegIP) in optimize_encoding()
4551 && i.index_reg->reg_num != RegIZ in optimize_encoding()
4594 unsigned int base_regnum = i.op[1].regs->reg_num; in optimize_encoding()
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/netbsd-src/external/gpl3/binutils.old/dist/gas/config/
H A Dtc-i386-intel.c290 int reg_num; in i386_intel_simplify_register() local
299 reg_num = e->X_add_number; in i386_intel_simplify_register()
301 reg_num = e->X_md - 1; in i386_intel_simplify_register()
303 if (reg_num < 0 || reg_num >= (int) i386_regtab_size) in i386_intel_simplify_register()
309 if (!check_register (&i386_regtab[reg_num])) in i386_intel_simplify_register()
312 register_prefix, i386_regtab[reg_num].reg_name); in i386_intel_simplify_register()
323 if (i386_regtab[reg_num].reg_type.bitfield.class == SReg in i386_intel_simplify_register()
324 && i386_regtab[reg_num].reg_num == RegFlat) in i386_intel_simplify_register()
329 i.op[this_operand].regs = i386_regtab + reg_num; in i386_intel_simplify_register()
332 && (i386_regtab[reg_num].reg_type.bitfield.xmmword in i386_intel_simplify_register()
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H A Dtc-i386.c2204 unsigned int nr = r->reg_num; in register_number()
3000 switch (regtab->reg_num) in md_begin()
3009 if (!regtab->reg_num) in md_begin()
3796 register_specifier = i.vex.register_specifier->reg_num; in build_evex_prefix()
3956 i.vex.bytes[3] |= i.mask.reg->reg_num; in build_evex_prefix()
4171 if (!i.index_reg && i.base_reg->reg_num != RegIP) in optimize_encoding()
4174 && i.index_reg->reg_num != RegIZ in optimize_encoding()
4220 unsigned int base_regnum = i.op[1].regs->reg_num; in optimize_encoding()
5172 if (i.op[x].regs->reg_num > 3) in md_assemble()
5196 && i.op[x].regs->reg_num > 3) in md_assemble()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddm_services.h185 #define get_reg_field_value_soc15(reg_value, block, reg_num, reg_name, reg_field)\ argument
188 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
189 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
191 #define set_reg_field_value_soc15(reg_value, value, block, reg_num, reg_name, reg_field)\ argument
195 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## _MASK,\
196 block ## reg_num ## _ ## reg_name ## __ ## reg_field ## __SHIFT)
/netbsd-src/external/gpl3/binutils.old/dist/gprofng/common/
H A Dhwcdrv.c67 regno_t regno = entries[idx]->reg_num; in hwcdrv_assign_all_regnos()
81 entries[idx]->reg_num = regno; /* assigning back to entries */ in hwcdrv_assign_all_regnos()
89 if (entries[idx]->reg_num == REGNO_ANY) in hwcdrv_assign_all_regnos()
104 entries[idx]->reg_num = regno; /* assigning back to entries */ in hwcdrv_assign_all_regnos()
407 unsigned int reg_num; // PMC assignment, potentially for detecting conflicts member
1274 if (hwcfuncs_get_x86_eventsel (hwcdef[idx].reg_num, in hwcdrv_create_counters()
1280 glb_event_def->reg_num = pmc_sel; in hwcdrv_create_counters()
1290 (long long) glb_event_def->min_time, (int) glb_event_def->reg_num, in hwcdrv_create_counters()
H A Dhwcfuncs.c166 hdr, phwcdef->name, phwcdef->int_name, phwcdef->reg_num, in ctrdefprint()
238 hwcdef[idx].reg_num = REGNO_ANY; in clear_hwcdefs()
317 hwcdef[idx].reg_num = reg; in process_data_descriptor()
H A Dhwcentry.h109 regno_t reg_num; /* register in CPU, aka picnum, or REGNO_ANY */ member
H A Dhwctable.c2784 pentry->reg_num, in hwcentry_print()
3038 if (!regno_is_valid (pctr, pctr->reg_num)) in stdlist_print()
3050 if (ii > 1 && pctr->reg_num != REGNO_ANY) in stdlist_print()
3146 if (pentry->reg_num != REGNO_ANY) in check_tables()
3173 if (pentry->reg_num != REGNO_ANY && pentry->reg_num != REGNO_INVALID) in check_tables()
3176 pentry->reg_num, cputag, pentry->name); in check_tables()
3177 if (pentry->reg_num == REGNO_INVALID) in check_tables()
3188 if (pentry->reg_num == REGNO_ANY) in check_tables()
3763 if (pret_ctr->reg_num == REGNO_ANY) in process_ctr_def()
3768 pret_ctr->reg_num = pfound->reg_list[0]; in process_ctr_def()
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/netbsd-src/external/gpl3/binutils/dist/gprofng/common/
H A Dhwcdrv.c67 regno_t regno = entries[idx]->reg_num; in hwcdrv_assign_all_regnos()
81 entries[idx]->reg_num = regno; /* assigning back to entries */ in hwcdrv_assign_all_regnos()
89 if (entries[idx]->reg_num == REGNO_ANY) in hwcdrv_assign_all_regnos()
104 entries[idx]->reg_num = regno; /* assigning back to entries */ in hwcdrv_assign_all_regnos()
407 unsigned int reg_num; // PMC assignment, potentially for detecting conflicts member
1269 if (hwcfuncs_get_x86_eventsel (hwcdef[idx].reg_num, in hwcdrv_create_counters()
1275 glb_event_def->reg_num = pmc_sel; in hwcdrv_create_counters()
1285 (long long) glb_event_def->min_time, (int) glb_event_def->reg_num, in hwcdrv_create_counters()
H A Dhwcfuncs.c166 hdr, phwcdef->name, phwcdef->int_name, phwcdef->reg_num, in ctrdefprint()
238 hwcdef[idx].reg_num = REGNO_ANY; in clear_hwcdefs()
330 hwcdef[idx].reg_num = reg; in process_data_descriptor()
H A Dhwcentry.h109 regno_t reg_num; /* register in CPU, aka picnum, or REGNO_ANY */ member
H A Dhwctable.c2372 .val = PRELOAD_DEF, .reg_num = REGNO_ANY
2820 pentry->reg_num, in hwcentry_print()
3074 if (!regno_is_valid (pctr, pctr->reg_num)) in stdlist_print()
3086 if (ii > 1 && pctr->reg_num != REGNO_ANY) in stdlist_print()
3182 if (pentry->reg_num != REGNO_ANY) in check_tables()
3209 if (pentry->reg_num != REGNO_ANY && pentry->reg_num != REGNO_INVALID) in check_tables()
3212 pentry->reg_num, cputag, pentry->name); in check_tables()
3213 if (pentry->reg_num == REGNO_INVALID) in check_tables()
3224 if (pentry->reg_num == REGNO_ANY) in check_tables()
3799 if (pret_ctr->reg_num == REGNO_ANY) in process_ctr_def()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dce120/
H A Damdgpu_hw_factory_dce120.c48 #define reg_num 0 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn10/
H A Damdgpu_hw_factory_dcn10.c49 #define reg_num 0 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn21/
H A Damdgpu_hw_factory_dcn21.c53 #define reg_num 0 macro
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/gpio/dcn20/
H A Damdgpu_hw_factory_dcn20.c55 #define reg_num 0 macro

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