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Searched refs:reg_base (Results 1 – 25 of 27) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Dinterrupt.c159 if (i915_mmio_reg_offset(irq->info[i]->reg_base) == reg) in regbase_to_irq_info()
334 regbase_to_iir(i915_mmio_reg_offset(info->reg_base))) in update_upstream_irq()
336 regbase_to_ier(i915_mmio_reg_offset(info->reg_base))); in update_upstream_irq()
362 u32 isr = i915_mmio_reg_offset(up_irq_info->reg_base); in update_upstream_irq()
368 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
370 i915_mmio_reg_offset(up_irq_info->reg_base)); in update_upstream_irq()
409 unsigned int reg_base; in propagate_event() local
416 reg_base = i915_mmio_reg_offset(info->reg_base); in propagate_event()
420 regbase_to_imr(reg_base)))) { in propagate_event()
423 regbase_to_iir(reg_base))); in propagate_event()
[all …]
H A Dinterrupt.h180 i915_reg_t reg_base; member
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dnios2-dis.c280 struct nios2_reg *reg_base; in nios2_print_insn_arg() local
303 reg_base = nios2_control_regs (); in nios2_print_insn_arg()
304 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); in nios2_print_insn_arg()
308 reg_base = nios2_regs; in nios2_print_insn_arg()
317 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
326 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
335 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); in nios2_print_insn_arg()
341 reg_base = nios2_regs; in nios2_print_insn_arg()
353 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
377 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
[all …]
H A Dtic6x-dis.c819 unsigned int reg_base = 0; in print_insn_tic6x() local
929 reg_base = 16; in print_insn_tic6x()
941 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
947 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
958 snprintf (operands[op_num], 24, "b%u", reg_base + fld_val); in print_insn_tic6x()
969 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
975 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
984 reg_side, reg_base + fld_val + 1, in print_insn_tic6x()
985 reg_side, reg_base + fld_val); in print_insn_tic6x()
994 reg_side, reg_base + fld_val + 1, in print_insn_tic6x()
[all …]
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dnios2-dis.c280 struct nios2_reg *reg_base; in nios2_print_insn_arg() local
303 reg_base = nios2_control_regs (); in nios2_print_insn_arg()
304 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); in nios2_print_insn_arg()
308 reg_base = nios2_regs; in nios2_print_insn_arg()
317 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
326 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
335 (*info->fprintf_func) (info->stream, "%s", reg_base[i].name); in nios2_print_insn_arg()
341 reg_base = nios2_regs; in nios2_print_insn_arg()
353 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
377 reg_base = nios2_coprocessor_regs (); in nios2_print_insn_arg()
[all …]
H A Dtic6x-dis.c819 unsigned int reg_base = 0; in print_insn_tic6x() local
929 reg_base = 16; in print_insn_tic6x()
941 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
947 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
958 snprintf (operands[op_num], 24, "b%u", reg_base + fld_val); in print_insn_tic6x()
969 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
975 snprintf (operands[op_num], 24, "%c%u", reg_side, reg_base + fld_val); in print_insn_tic6x()
984 reg_side, reg_base + fld_val + 1, in print_insn_tic6x()
985 reg_side, reg_base + fld_val); in print_insn_tic6x()
994 reg_side, reg_base + fld_val + 1, in print_insn_tic6x()
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/avr/
H A Davr.c4100 int reg_base = true_regnum (base); in avr_out_movhi_r_mr_reg_no_disp_tiny() local
4102 if (reg_dest == reg_base) /* R = (R) */ in avr_out_movhi_r_mr_reg_no_disp_tiny()
4127 int reg_base = true_regnum (XEXP (base, 0)); in avr_out_movhi_r_mr_reg_disp_tiny() local
4129 if (reg_base == reg_dest) in avr_out_movhi_r_mr_reg_disp_tiny()
4185 int reg_base = true_regnum (base); in out_movhi_r_mr() local
4190 if (reg_base > 0) in out_movhi_r_mr()
4195 if (reg_dest == reg_base) /* R = (R) */ in out_movhi_r_mr()
4200 if (reg_base != REG_X) in out_movhi_r_mr()
4215 int reg_base = true_regnum (XEXP (base, 0)); in out_movhi_r_mr() local
4243 if (reg_base == REG_X) in out_movhi_r_mr()
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/avr/
H A Davr.cc4307 int reg_base = true_regnum (base); in avr_out_movhi_r_mr_reg_no_disp_tiny() local
4309 if (reg_dest == reg_base) /* R = (R) */ in avr_out_movhi_r_mr_reg_no_disp_tiny()
4334 int reg_base = true_regnum (XEXP (base, 0)); in avr_out_movhi_r_mr_reg_disp_tiny() local
4336 if (reg_base == reg_dest) in avr_out_movhi_r_mr_reg_disp_tiny()
4392 int reg_base = true_regnum (base); in out_movhi_r_mr() local
4397 if (reg_base > 0) in out_movhi_r_mr()
4402 if (reg_dest == reg_base) /* R = (R) */ in out_movhi_r_mr()
4407 if (reg_base != REG_X) in out_movhi_r_mr()
4422 int reg_base = true_regnum (XEXP (base, 0)); in out_movhi_r_mr() local
4450 if (reg_base == REG_X) in out_movhi_r_mr()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Dintel_wopcm.c206 u32 reg_base = intel_uncore_read(uncore, DMA_GUC_WOPCM_OFFSET); in __wopcm_regs_locked() local
210 !(reg_base & GUC_WOPCM_OFFSET_VALID)) in __wopcm_regs_locked()
213 *guc_wopcm_base = reg_base & GUC_WOPCM_OFFSET_MASK; in __wopcm_regs_locked()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_gfx.c121 *reg = adev->gfx.scratch.reg_base + i; in amdgpu_gfx_scratch_get()
137 adev->gfx.scratch.free_mask |= 1u << (reg - adev->gfx.scratch.reg_base); in amdgpu_gfx_scratch_free()
H A Damdgpu_gfx.h107 uint32_t reg_base; member
H A Damdgpu_gfx_v6_0.c1790 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v6_0_scratch_init()
H A Damdgpu_gfx_v7_0.c2080 adev->gfx.scratch.reg_base = mmSCRATCH_REG0; in gfx_v7_0_scratch_init()
H A Damdgpu_gfx_v10_0.c421 adev->gfx.scratch.reg_base = SOC15_REG_OFFSET(GC, 0, mmSCRATCH_REG0); in gfx_v10_0_scratch_init()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_device.c283 rdev->scratch.reg_base = RADEON_SCRATCH_REG0; in radeon_scratch_init()
286 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in radeon_scratch_init()
H A Dradeon_fence.c914 rdev->scratch.reg_base; in radeon_fence_driver_start_ring()
H A Dradeon_r600.c2848 rdev->scratch.reg_base = SCRATCH_REG0; in r600_scratch_init()
2851 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in r600_scratch_init()
H A Dradeon_si.c3374 rdev->scratch.reg_base = SCRATCH_REG0; in si_scratch_init()
3377 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in si_scratch_init()
H A Dradeon.h743 uint32_t reg_base; member
H A Dradeon_cik.c3454 rdev->scratch.reg_base = SCRATCH_REG0; in cik_scratch_init()
3457 rdev->scratch.reg[i] = rdev->scratch.reg_base + (i * 4); in cik_scratch_init()
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/
H A Dtegra132.dtsi865 reg = <0x0 0x700e2000 0x0 0x600>, /* 0: SOC_THERM reg_base */
866 <0x0 0x70040000 0x0 0x200>; /* 2: CCROC reg_base */
H A Dtegra210.dtsi1314 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
1315 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm/boot/dts/
H A Dtegra124.dtsi930 reg = <0x0 0x700e2000 0x0 0x600>, /* SOC_THERM reg_base */
931 <0x0 0x60006000 0x0 0x400>; /* CAR reg_base */
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Darm.c26325 int n_free, reg_base, size; in thumb1_extra_regs_pushed() local
26360 reg_base = 0; in thumb1_extra_regs_pushed()
26365 reg_base = ARM_NUM_INTS (size); in thumb1_extra_regs_pushed()
26366 live_regs_mask >>= reg_base; in thumb1_extra_regs_pushed()
26369 while (reg_base + n_free < 8 && !(live_regs_mask & 1) in thumb1_extra_regs_pushed()
26370 && (for_prologue || call_used_or_fixed_reg_p (reg_base + n_free))) in thumb1_extra_regs_pushed()
27794 int reg_base = REGNO (base); in thumb_load_double_from_address() local
27800 reg_dest + 1, reg_base, reg_offset); in thumb_load_double_from_address()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Darm.cc26577 int n_free, reg_base, size; in thumb1_extra_regs_pushed() local
26612 reg_base = 0; in thumb1_extra_regs_pushed()
26617 reg_base = ARM_NUM_INTS (size); in thumb1_extra_regs_pushed()
26618 live_regs_mask >>= reg_base; in thumb1_extra_regs_pushed()
26621 while (reg_base + n_free < 8 && !(live_regs_mask & 1) in thumb1_extra_regs_pushed()
26622 && (for_prologue || call_used_or_fixed_reg_p (reg_base + n_free))) in thumb1_extra_regs_pushed()
28094 int reg_base = REGNO (base); in thumb_load_double_from_address() local
28100 reg_dest + 1, reg_base, reg_offset); in thumb_load_double_from_address()

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