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Searched refs:regClass (Results 1 – 3 of 3) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DFLATInstructions.td142 class FLAT_Load_Pseudo <string opName, RegisterClass regClass,
145 RegisterOperand vdata_op = getLdStRegisterOperand<regClass>.ret> : FLAT_Pseudo<
188 multiclass FLAT_Global_Load_Pseudo<string opName, RegisterClass regClass, bit HasTiedInput = 0> {
190 def "" : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1>,
192 def _SADDR : FLAT_Load_Pseudo<opName, regClass, HasTiedInput, 1, 1>,
197 class FLAT_Global_Load_AddTid_Pseudo <string opName, RegisterClass regClass,
200 (outs regClass:$vdst),
203 !if(HasTiedOutput, (ins regClass:$vdst_in), (ins))),
218 multiclass FLAT_Global_Load_AddTid_Pseudo<string opName, RegisterClass regClass,
220 def "" : FLAT_Global_Load_AddTid_Pseudo<opName, regClass, HasTiedOutput, HasSignedOffset>,
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H A DSIWholeQuadMode.cpp1431 const TargetRegisterClass *regClass = in lowerCopyInstrs() local
1434 regClass = TRI->getSubRegClass(regClass, SubReg); in lowerCopyInstrs()
1436 const unsigned MovOp = TII->getMovOpcode(regClass); in lowerCopyInstrs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.h658 int16_t regClass = Desc.OpInfo[OpNo].RegClass; in getRegNumForOperand() local
659 switch (regClass) { in getRegNumForOperand()