| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/hwmgr/ |
| H A D | amdgpu_vega20_processpptables.c | 72 static void dump_pptable(PPTable_t *pptable)
76 pr_info("Version = 0x%08x\n", pptable->Version);
78 pr_info("FeaturesToRun[0] = 0x%08x\n", pptable->FeaturesToRun[0]);
79 pr_info("FeaturesToRun[1] = 0x%08x\n", pptable->FeaturesToRun[1]);
81 pr_info("SocketPowerLimitAc0 = %d\n", pptable->SocketPowerLimitAc0);
82 pr_info("SocketPowerLimitAc0Tau = %d\n", pptable->SocketPowerLimitAc0Tau);
83 pr_info("SocketPowerLimitAc1 = %d\n", pptable->SocketPowerLimitAc1);
84 pr_info("SocketPowerLimitAc1Tau = %d\n", pptable->SocketPowerLimitAc1Tau);
85 pr_info("SocketPowerLimitAc2 = %d\n", pptable->SocketPowerLimitAc2);
86 pr_info("SocketPowerLimitAc2Tau = %d\n", pptable->SocketPowerLimitAc2Tau);
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| H A D | amdgpu_process_pptables_v1_0.c | 214 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_platform_power_management_table()
257 …t phm_ppt_v1_information *pp_table_information = (struct phm_ppt_v1_information *)(hwmgr->pptable); in init_dpm_2_parameters()
505 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_pcie_table()
743 (struct phm_ppt_v1_information *)(hwmgr->pptable); in get_gpio_table()
775 (struct phm_ppt_v1_information *)(hwmgr->pptable); in init_clock_voltage_dependency()
1070 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v1_information), GFP_KERNEL); in pp_tables_v1_0_initialize()
1072 PP_ASSERT_WITH_CODE((NULL != hwmgr->pptable), in pp_tables_v1_0_initialize()
1117 (struct phm_ppt_v1_information *)(hwmgr->pptable); in pp_tables_v1_0_uninitialize()
1155 kfree(hwmgr->pptable); in pp_tables_v1_0_uninitialize()
1156 hwmgr->pptable = NULL; in pp_tables_v1_0_uninitialize()
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| H A D | amdgpu_vega12_processpptables.c | 201 (struct phm_ppt_v3_information *)hwmgr->pptable; in init_powerplay_table_information()
276 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v3_information), GFP_KERNEL); in vega12_pp_tables_initialize()
277 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), in vega12_pp_tables_initialize()
303 (struct phm_ppt_v3_information *)(hwmgr->pptable); in vega12_pp_tables_uninitialize()
320 kfree(hwmgr->pptable); in vega12_pp_tables_uninitialize()
321 hwmgr->pptable = NULL; in vega12_pp_tables_uninitialize()
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| H A D | amdgpu_vega10_hwmgr.c | 202 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_set_features_platform_caps()
312 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_odn_initial_default_setting()
529 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_get_socclk_for_voltage_evv()
566 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_get_evv_voltages()
671 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_patch_voltage_dependency_tables_with_lookup_table()
747 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_complete_dependency_tables()
776 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_set_private_data_based_on_pptable()
1168 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega10_construct_voltage_tables()
1257 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_setup_default_pcie_table()
1305 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_setup_default_dpm_tables()
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| H A D | amdgpu_vega10_processpptables.c | 818 (struct phm_ppt_v2_information *)(hwmgr->pptable); in get_pcie_table()
913 (struct phm_ppt_v2_information *)(hwmgr->pptable); in init_powerplay_extended_tables()
1105 (struct phm_ppt_v2_information *)(hwmgr->pptable); in init_dpm_2_parameters()
1192 hwmgr->pptable = kzalloc(sizeof(struct phm_ppt_v2_information), GFP_KERNEL); in vega10_pp_tables_initialize()
1194 PP_ASSERT_WITH_CODE((hwmgr->pptable != NULL), in vega10_pp_tables_initialize()
1239 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_pp_tables_uninitialize()
1277 kfree(hwmgr->pptable); in vega10_pp_tables_uninitialize()
1278 hwmgr->pptable = NULL; in vega10_pp_tables_uninitialize()
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| H A D | amdgpu_smu7_hwmgr.c | 263 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_construct_voltage_tables()
540 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_default_pcie_table()
767 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_dpm_tables_v1()
833 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_odn_initial_default_setting()
878 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_setup_voltage_range_from_vbios()
906 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_check_dpm_table_updated()
1562 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_init_dpm_defaults()
1711 (struct phm_ppt_v1_information *)hwmgr->pptable; in smu7_get_evv_voltages()
1844 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_patch_clock_voltage_limits_with_vddc_leakage()
1858 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_patch_voltage_dependency_tables_with_lookup_table()
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| H A D | amdgpu_smu_helper.c | 471 (struct phm_ppt_v1_information *)(hwmgr->pptable); in phm_get_sclk_for_voltage_evv()
501 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); in phm_initializa_dynamic_state_adjustment_rule_settings()
541 (struct phm_ppt_v1_information *)hwmgr->pptable; in phm_apply_dal_min_voltage_request()
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| H A D | amdgpu_vega20_hwmgr.c | 800 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_init_smc_table()
1023 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_od8_set_feature_capabilities()
1223 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_od8_initialize_default_settings()
2753 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega20_get_dal_power_level()
3269 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega20_print_clock_levels()
3270 PPTable_t *pptable = (PPTable_t *)pptable_information->smc_pptable; in vega20_print_clock_levels() local
3376 gen_speed = pptable->PcieGenSpeed[i]; in vega20_print_clock_levels()
3377 lane_width = pptable->PcieLaneCount[i]; in vega20_print_clock_levels()
3390 pptable->LclkFreq[i], in vega20_print_clock_levels()
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| H A D | amdgpu_smu10_hwmgr.c | 417 struct smu10_voltage_dependency_table **pptable, in smu10_get_clock_voltage_dependency_table() argument
437 *pptable = ptable; in smu10_get_clock_voltage_dependency_table()
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| H A D | amdgpu_vega10_powertune.c | 1294 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_initialize_power_tune_defaults()
1344 (struct phm_ppt_v2_information *)(hwmgr->pptable); in vega10_enable_power_containment()
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| H A D | amdgpu_smu7_powertune.c | 1118 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_enable_power_containment()
1203 (struct phm_ppt_v1_information *)(hwmgr->pptable); in smu7_power_control_set_level()
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| H A D | amdgpu_vega12_hwmgr.c | 742 (struct phm_ppt_v3_information *)hwmgr->pptable; in vega12_init_smc_table()
1690 (struct phm_ppt_v2_information *)hwmgr->pptable; in vega12_get_dal_power_level()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/ |
| H A D | amdgpu_arcturus_ppt.c | 859 PPTable_t *pptable = smu->smu_table.driver_pptable; in arcturus_get_thermal_temperature_range() local
864 range->max = pptable->TedgeLimit * in arcturus_get_thermal_temperature_range()
866 range->edge_emergency_max = (pptable->TedgeLimit + CTF_OFFSET_EDGE) * in arcturus_get_thermal_temperature_range()
868 range->hotspot_crit_max = pptable->ThotspotLimit * in arcturus_get_thermal_temperature_range()
870 range->hotspot_emergency_max = (pptable->ThotspotLimit + CTF_OFFSET_HOTSPOT) * in arcturus_get_thermal_temperature_range()
872 range->mem_crit_max = pptable->TmemLimit * in arcturus_get_thermal_temperature_range()
874 range->mem_emergency_max = (pptable->TmemLimit + CTF_OFFSET_HBM)* in arcturus_get_thermal_temperature_range()
991 PPTable_t *pptable = table_context->driver_pptable; in arcturus_read_sensor() local
1000 *(uint32_t *)data = pptable->FanMaximumRpm; in arcturus_read_sensor()
1050 PPTable_t *pptable = smu->smu_table.driver_pptable; in arcturus_get_fan_speed_percent() local
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| H A D | amdgpu_vega20_ppt.c | 966 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; in vega20_print_clk_levels() local
1078 (pptable->PcieGenSpeed[i] == 0) ? "2.5GT/s," : in vega20_print_clk_levels()
1079 (pptable->PcieGenSpeed[i] == 1) ? "5.0GT/s," : in vega20_print_clk_levels()
1080 (pptable->PcieGenSpeed[i] == 2) ? "8.0GT/s," : in vega20_print_clk_levels()
1081 (pptable->PcieGenSpeed[i] == 3) ? "16.0GT/s," : "", in vega20_print_clk_levels()
1082 (pptable->PcieLaneCount[i] == 1) ? "x1" : in vega20_print_clk_levels()
1083 (pptable->PcieLaneCount[i] == 2) ? "x2" : in vega20_print_clk_levels()
1084 (pptable->PcieLaneCount[i] == 3) ? "x4" : in vega20_print_clk_levels()
1085 (pptable->PcieLaneCount[i] == 4) ? "x8" : in vega20_print_clk_levels()
1086 (pptable->PcieLaneCount[i] == 5) ? "x12" : in vega20_print_clk_levels()
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| H A D | amdgpu_navi10_ppt.c | 737 PPTable_t *pptable = smu->smu_table.driver_pptable; in navi10_is_support_fine_grained_dpm() local
742 dpm_desc = &pptable->DpmDescriptor[clk_index]; in navi10_is_support_fine_grained_dpm()
776 PPTable_t *pptable = (PPTable_t *)table_context->driver_pptable; in navi10_print_clk_levels() local
850 pptable->LclkFreq[i], in navi10_print_clk_levels()
1229 PPTable_t *pptable = smu->smu_table.driver_pptable; in navi10_get_fan_speed_percent() local
1235 percent = current_rpm * 100 / pptable->FanMaximumRpm; in navi10_get_fan_speed_percent()
1600 PPTable_t *pptable = table_context->driver_pptable; in navi10_read_sensor() local
1608 *(uint32_t *)data = pptable->FanMaximumRpm; in navi10_read_sensor()
1847 PPTable_t *pptable = smu->smu_table.driver_pptable; in navi10_get_pptable_power_limit() local
1848 return pptable->SocketPowerLimitAc[PPT_THROTTLER_PPT0]; in navi10_get_pptable_power_limit()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/ |
| H A D | amdgpu_vegam_smumgr.c | 341 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_uvd_smc_table()
373 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_vce_smc_table()
404 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_update_bif_smc_table()
439 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_initialize_power_tune_defaults()
511 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_cac_table()
548 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_ulv_level()
819 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_single_graphic_level()
872 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_all_graphic_levels()
988 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_single_memory_level()
1092 (struct phm_ppt_v1_information *)(hwmgr->pptable); in vegam_populate_mvdd_value()
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| H A D | amdgpu_fiji_smumgr.c | 478 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_initialize_power_tune_defaults()
500 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_bapm_parameters_in_dpm_table()
594 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_tdc_limit()
680 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_bapm_vddc_base_leakage_sidd()
768 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_cac_table()
808 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_ulv_level()
951 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_single_graphic_level()
1013 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_all_graphic_levels()
1173 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_single_memory_level()
1283 (struct phm_ppt_v1_information *)(hwmgr->pptable); in fiji_populate_mvdd_value()
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| H A D | amdgpu_polaris10_smumgr.c | 436 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_bapm_parameters_in_dpm_table()
495 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_tdc_limit()
575 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_bapm_vddc_base_leakage_sidd()
710 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_cac_table()
744 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_ulv_level()
919 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_single_graphic_level()
988 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_all_graphic_levels()
1081 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_single_memory_level()
1184 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_mvdd_value()
1211 (struct phm_ppt_v1_information *)(hwmgr->pptable); in polaris10_populate_smc_acpi_level()
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| H A D | amdgpu_tonga_smumgr.c | 258 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_get_dependency_volt_by_clk()
403 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_cac_tables()
488 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_ulv_level()
629 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_single_graphic_level()
695 struct phm_ppt_v1_information *pptable_info = (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_all_graphic_levels()
972 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_single_memory_level()
1153 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_mvdd_value()
1321 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_smc_uvd_level()
1381 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_smc_vce_level()
1426 (struct phm_ppt_v1_information *)(hwmgr->pptable); in tonga_populate_smc_acp_level()
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| /netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/inc/ |
| H A D | hwmgr.h | 764 void *pptable; member
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