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Searched refs:pipe (Results 1 – 25 of 1236) sorted by relevance

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/netbsd-src/sys/kern/
H A Dsys_pipe.c129 static void pipeclose(struct pipe *);
130 static void pipe_free_kmem(struct pipe *);
131 static int pipe_create(struct pipe **, pool_cache_t, struct timespec *);
132 static int pipelock(struct pipe *, bool);
133 static inline void pipeunlock(struct pipe *);
134 static void pipeselwakeup(struct pipe *, struct pipe *, int);
135 static int pipespace(struct pipe *, int);
147 pipe_wr_cache = pool_cache_init(sizeof(struct pipe), 0, 0, 0, "pipewr", in pipe_init()
152 pipe_rd_cache = pool_cache_init(sizeof(struct pipe), 0, 0, 0, "piperd", in pipe_init()
160 struct pipe *pipe; in pipe_ctor() local
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/netbsd-src/sys/external/bsd/drm2/dist/drm/
H A Ddrm_vblank.c93 drm_get_last_vbltimestamp(struct drm_device *dev, unsigned int pipe,
105 static void store_vblank(struct drm_device *dev, unsigned int pipe, in store_vblank() argument
109 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in store_vblank()
121 static u32 drm_max_vblank_count(struct drm_device *dev, unsigned int pipe) in drm_max_vblank_count() argument
123 struct drm_vblank_crtc *vblank = &dev->vblank[pipe]; in drm_max_vblank_count()
132 static u32 drm_vblank_no_hw_counter(struct drm_device *dev, unsigned int pipe) in drm_vblank_no_hw_counter() argument
134 WARN_ON_ONCE(drm_max_vblank_count(dev, pipe) != 0); in drm_vblank_no_hw_counter()
138 static u32 __get_vblank_counter(struct drm_device *dev, unsigned int pipe) in __get_vblank_counter() argument
141 struct drm_crtc *crtc = drm_crtc_from_index(dev, pipe); in __get_vblank_counter()
151 return dev->driver->get_vblank_counter(dev, pipe); in __get_vblank_counter()
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/netbsd-src/external/ibm-public/postfix/dist/src/pipe/
H A DMakefile.in2 SRCS = pipe.c
3 OBJS = pipe.o
9 PROG = pipe
62 pipe.o: ../../include/argv.h
63 pipe.o: ../../include/attr.h
64 pipe.o: ../../include/bounce.h
65 pipe.o: ../../include/canon_addr.h
66 pipe.o: ../../include/check_arg.h
67 pipe.o: ../../include/defer.h
68 pipe.o: ../../include/deliver_completed.h
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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/display/
H A Dintel_fifo_underrun.c63 enum pipe pipe; in ivb_can_enable_err_int() local
67 for_each_pipe(dev_priv, pipe) { in ivb_can_enable_err_int()
68 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in ivb_can_enable_err_int()
80 enum pipe pipe; in cpt_can_enable_serr_int() local
85 for_each_pipe(dev_priv, pipe) { in cpt_can_enable_serr_int()
86 crtc = intel_get_crtc_for_pipe(dev_priv, pipe); in cpt_can_enable_serr_int()
98 i915_reg_t reg = PIPESTAT(crtc->pipe); in i9xx_check_fifo_underruns()
106 enable_mask = i915_pipestat_enable_mask(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
110 trace_intel_cpu_fifo_underrun(dev_priv, crtc->pipe); in i9xx_check_fifo_underruns()
111 DRM_ERROR("pipe %c underrun\n", pipe_name(crtc->pipe)); in i9xx_check_fifo_underruns()
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H A Dintel_dpio_phy.c653 enum pipe pipe = intel_crtc->pipe; in chv_set_phy_signal_level() local
660 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW10(ch)); in chv_set_phy_signal_level()
664 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW10(ch), val); in chv_set_phy_signal_level()
667 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW10(ch)); in chv_set_phy_signal_level()
671 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW10(ch), val); in chv_set_phy_signal_level()
674 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS01_DW9(ch)); in chv_set_phy_signal_level()
677 vlv_dpio_write(dev_priv, pipe, VLV_PCS01_DW9(ch), val); in chv_set_phy_signal_level()
680 val = vlv_dpio_read(dev_priv, pipe, VLV_PCS23_DW9(ch)); in chv_set_phy_signal_level()
683 vlv_dpio_write(dev_priv, pipe, VLV_PCS23_DW9(ch), val); in chv_set_phy_signal_level()
688 val = vlv_dpio_read(dev_priv, pipe, CHV_TX_DW4(ch, i)); in chv_set_phy_signal_level()
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H A Dintel_color.c163 enum pipe pipe = crtc->pipe; in ilk_update_pipe_csc() local
165 I915_WRITE(PIPE_CSC_PREOFF_HI(pipe), preoff[0]); in ilk_update_pipe_csc()
166 I915_WRITE(PIPE_CSC_PREOFF_ME(pipe), preoff[1]); in ilk_update_pipe_csc()
167 I915_WRITE(PIPE_CSC_PREOFF_LO(pipe), preoff[2]); in ilk_update_pipe_csc()
169 I915_WRITE(PIPE_CSC_COEFF_RY_GY(pipe), coeff[0] << 16 | coeff[1]); in ilk_update_pipe_csc()
170 I915_WRITE(PIPE_CSC_COEFF_BY(pipe), coeff[2] << 16); in ilk_update_pipe_csc()
172 I915_WRITE(PIPE_CSC_COEFF_RU_GU(pipe), coeff[3] << 16 | coeff[4]); in ilk_update_pipe_csc()
173 I915_WRITE(PIPE_CSC_COEFF_BU(pipe), coeff[5] << 16); in ilk_update_pipe_csc()
175 I915_WRITE(PIPE_CSC_COEFF_RV_GV(pipe), coeff[6] << 16 | coeff[7]); in ilk_update_pipe_csc()
176 I915_WRITE(PIPE_CSC_COEFF_BV(pipe), coeff[8] << 16); in ilk_update_pipe_csc()
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H A Dintel_vdsc.c348 enum pipe pipe = crtc->pipe; in intel_dsc_source_support() local
358 (pipe != PIPE_A || in intel_dsc_source_support()
382 WARN_ON(crtc->pipe == PIPE_A); in is_pipe_dsc()
479 enum pipe pipe = crtc->pipe; in intel_dsc_power_domain() local
492 if (INTEL_GEN(i915) >= 12 && pipe == PIPE_A) in intel_dsc_power_domain()
495 return POWER_DOMAIN_PIPE(pipe); in intel_dsc_power_domain()
506 enum pipe pipe = crtc->pipe; in intel_dsc_pps_configure() local
536 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_0(pipe), pps_val); in intel_dsc_pps_configure()
538 I915_WRITE(ICL_DSC1_PICTURE_PARAMETER_SET_0(pipe), in intel_dsc_pps_configure()
555 I915_WRITE(ICL_DSC0_PICTURE_PARAMETER_SET_1(pipe), pps_val); in intel_dsc_pps_configure()
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H A Dintel_sprite.c136 pipe_name(crtc->pipe), ret ? ret : -EWOULDBLOCK); in intel_pipe_update_start()
179 enum pipe pipe = crtc->pipe; in intel_pipe_update_end() local
209 pipe_name(pipe), crtc->debug.start_vbl_count, in intel_pipe_update_end()
219 pipe_name(pipe), in intel_pipe_update_end()
384 enum pipe pipe = plane->pipe; in skl_program_scaler() local
421 I915_WRITE_FW(SKL_PS_CTRL(pipe, scaler_id), in skl_program_scaler()
423 I915_WRITE_FW(SKL_PS_VPHASE(pipe, scaler_id), in skl_program_scaler()
425 I915_WRITE_FW(SKL_PS_HPHASE(pipe, scaler_id), in skl_program_scaler()
427 I915_WRITE_FW(SKL_PS_WIN_POS(pipe, scaler_id), (crtc_x << 16) | crtc_y); in skl_program_scaler()
428 I915_WRITE_FW(SKL_PS_WIN_SZ(pipe, scaler_id), (crtc_w << 16) | crtc_h); in skl_program_scaler()
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H A Dintel_pipe_crc.c79 enum pipe pipe, in i9xx_pipe_crc_auto_source() argument
97 if (crtc->pipe != pipe) in i9xx_pipe_crc_auto_source()
133 enum pipe pipe, in vlv_pipe_crc_ctl_reg() argument
140 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); in vlv_pipe_crc_ctl_reg()
183 switch (pipe) { in vlv_pipe_crc_ctl_reg()
203 enum pipe pipe, in i9xx_pipe_crc_ctl_reg() argument
208 int ret = i9xx_pipe_crc_auto_source(dev_priv, pipe, source); in i9xx_pipe_crc_ctl_reg()
243 enum pipe pipe) in vlv_undo_pipe_scramble_reset() argument
247 switch (pipe) { in vlv_undo_pipe_scramble_reset()
321 pipe_config->hw.active && crtc->pipe == PIPE_A && in intel_crtc_crc_setup_workarounds()
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H A Dintel_dsb.c48 enum pipe pipe = crtc->pipe; in is_dsb_busy() local
50 return DSB_STATUS & I915_READ(DSB_CTRL(pipe, dsb->id)); in is_dsb_busy()
57 enum pipe pipe = crtc->pipe; in intel_dsb_enable_engine() local
60 dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id)); in intel_dsb_enable_engine()
67 I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl); in intel_dsb_enable_engine()
69 POSTING_READ(DSB_CTRL(pipe, dsb->id)); in intel_dsb_enable_engine()
77 enum pipe pipe = crtc->pipe; in intel_dsb_disable_engine() local
80 dsb_ctrl = I915_READ(DSB_CTRL(pipe, dsb->id)); in intel_dsb_disable_engine()
87 I915_WRITE(DSB_CTRL(pipe, dsb->id), dsb_ctrl); in intel_dsb_disable_engine()
89 POSTING_READ(DSB_CTRL(pipe, dsb->id)); in intel_dsb_disable_engine()
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H A Dintel_display.c527 skl_wa_827(struct drm_i915_private *dev_priv, enum pipe pipe, bool enable) in skl_wa_827() argument
530 I915_WRITE(CLKGATE_DIS_PSL(pipe), in skl_wa_827()
531 I915_READ(CLKGATE_DIS_PSL(pipe)) | in skl_wa_827()
534 I915_WRITE(CLKGATE_DIS_PSL(pipe), in skl_wa_827()
535 I915_READ(CLKGATE_DIS_PSL(pipe)) & in skl_wa_827()
541 icl_wa_scalerclkgating(struct drm_i915_private *dev_priv, enum pipe pipe, in icl_wa_scalerclkgating() argument
545 I915_WRITE(CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
546 I915_READ(CLKGATE_DIS_PSL(pipe)) | DPFR_GATING_DIS); in icl_wa_scalerclkgating()
548 I915_WRITE(CLKGATE_DIS_PSL(pipe), in icl_wa_scalerclkgating()
549 I915_READ(CLKGATE_DIS_PSL(pipe)) & ~DPFR_GATING_DIS); in icl_wa_scalerclkgating()
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H A Dintel_audio.c564 enum pipe pipe = crtc->pipe; in ilk_audio_codec_disable() local
571 pipe_name(pipe)); in ilk_audio_codec_disable()
577 aud_config = IBX_AUD_CFG(pipe); in ilk_audio_codec_disable()
580 aud_config = VLV_AUD_CFG(pipe); in ilk_audio_codec_disable()
583 aud_config = CPT_AUD_CFG(pipe); in ilk_audio_codec_disable()
612 enum pipe pipe = crtc->pipe; in ilk_audio_codec_enable() local
621 pipe_name(pipe), drm_eld_size(eld)); in ilk_audio_codec_enable()
634 hdmiw_hdmiedid = IBX_HDMIW_HDMIEDID(pipe); in ilk_audio_codec_enable()
635 aud_config = IBX_AUD_CFG(pipe); in ilk_audio_codec_enable()
636 aud_cntl_st = IBX_AUD_CNTL_ST(pipe); in ilk_audio_codec_enable()
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/netbsd-src/sys/dev/usb/
H A Dusbdi.c64 SDT_PROBE_DEFINE5(usb, device, pipe, open,
71 SDT_PROBE_DEFINE7(usb, device, pipe, open__intr,
80 SDT_PROBE_DEFINE2(usb, device, pipe, transfer__start,
83 SDT_PROBE_DEFINE3(usb, device, pipe, transfer__done,
87 SDT_PROBE_DEFINE2(usb, device, pipe, start,
91 SDT_PROBE_DEFINE1(usb, device, pipe, close, "struct usbd_pipe *"/*pipe*/);
92 SDT_PROBE_DEFINE1(usb, device, pipe, abort__start,
94 SDT_PROBE_DEFINE1(usb, device, pipe, abort__done,
96 SDT_PROBE_DEFINE1(usb, device, pipe, clear__endpoint__stall,
98 SDT_PROBE_DEFINE1(usb, device, pipe, clear__endpoint__toggle,
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/netbsd-src/sys/external/mit/xen-include-public/dist/xen/include/public/io/
H A Dusbif.h148 #define usbif_pipeportnum(pipe) ((pipe) & USBIF_PIPE_PORT_MASK) argument
149 #define usbif_setportnum_pipe(pipe, portnum) ((pipe) | (portnum)) argument
151 #define usbif_pipeunlink(pipe) ((pipe) & USBIF_PIPE_UNLINK) argument
152 #define usbif_pipesubmit(pipe) (!usbif_pipeunlink(pipe)) argument
153 #define usbif_setunlink_pipe(pipe) ((pipe) | USBIF_PIPE_UNLINK) argument
155 #define usbif_pipein(pipe) ((pipe) & USBIF_PIPE_DIR) argument
156 #define usbif_pipeout(pipe) (!usbif_pipein(pipe)) argument
158 #define usbif_pipedevice(pipe) \ argument
159 (((pipe) >> USBIF_PIPE_DEV_SHIFT) & USBIF_PIPE_DEV_MASK)
161 #define usbif_pipeendpoint(pipe) \ argument
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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/
H A Di915_reg.h231 #define _PIPE(pipe, a, b) _PICK_EVEN(pipe, a, b) argument
237 #define _MMIO_PIPE(pipe, a, b) _MMIO(_PIPE(pipe, a, b)) argument
245 #define _MMIO_PIPE3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
246 #define _MMIO_PORT3(pipe, a, b, c) _MMIO(_PICK(pipe, a, b, c)) argument
254 #define _MMIO_PIPE2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->pipe_offsets[pipe] - \ argument
261 #define _CURSOR2(pipe, reg) _MMIO(INTEL_INFO(dev_priv)->cursor_offsets[(pipe)] - \ argument
1168 #define GEN7_PIPE_DE_LOAD_SL(pipe) _MMIO_PIPE(pipe, _GEN7_PIPEA_DE_LOAD_SL, _GEN7_PIPEB_DE_LOAD_SL) argument
1246 #define _DP_SSC(val, pipe) ((val) << (2 * (pipe))) argument
1247 #define DP_SSC_MASK(pipe) _DP_SSC(0x3, (pipe)) argument
1248 #define DP_SSC_PWR_ON(pipe) _DP_SSC(0x0, (pipe)) argument
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H A Di915_irq.c369 enum pipe pipe, in bdw_update_pipe_irq() argument
382 new_val = dev_priv->de_irq_mask[pipe]; in bdw_update_pipe_irq()
386 if (new_val != dev_priv->de_irq_mask[pipe]) { in bdw_update_pipe_irq()
387 dev_priv->de_irq_mask[pipe] = new_val; in bdw_update_pipe_irq()
388 I915_WRITE(GEN8_DE_PIPE_IMR(pipe), dev_priv->de_irq_mask[pipe]); in bdw_update_pipe_irq()
389 POSTING_READ(GEN8_DE_PIPE_IMR(pipe)); in bdw_update_pipe_irq()
419 enum pipe pipe) in i915_pipestat_enable_mask() argument
421 u32 status_mask = dev_priv->pipestat_irq_mask[pipe]; in i915_pipestat_enable_mask()
454 pipe_name(pipe), enable_mask, status_mask); in i915_pipestat_enable_mask()
460 enum pipe pipe, u32 status_mask) in i915_enable_pipestat() argument
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H A Di915_irq.h30 enum pipe pipe);
32 i915_enable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
36 i915_disable_pipestat(struct drm_i915_private *dev_priv, enum pipe pipe,
59 enum pipe pipe,
63 enum pipe pipe, u32 bits) in bdw_enable_pipe_irq() argument
65 bdw_update_pipe_irq(dev_priv, pipe, bits, bits); in bdw_enable_pipe_irq()
68 enum pipe pipe, u32 bits) in bdw_disable_pipe_irq() argument
70 bdw_update_pipe_irq(dev_priv, pipe, bits, 0); in bdw_disable_pipe_irq()
106 bool i915_get_crtc_scanoutpos(struct drm_device *dev, unsigned int pipe,
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/calcs/
H A Damdgpu_dcn_calcs.c306 const struct pipe_ctx *pipe, in pipe_ctx_to_e2e_pipe_params() argument
310 if (pipe->top_pipe != NULL && pipe->top_pipe->plane_state == pipe->plane_state) in pipe_ctx_to_e2e_pipe_params()
312 else if (pipe->bottom_pipe != NULL && pipe->bottom_pipe->plane_state == pipe->plane_state) in pipe_ctx_to_e2e_pipe_params()
315 if (pipe->plane_res.dpp->ctx->dc->debug.optimized_watermark) { in pipe_ctx_to_e2e_pipe_params()
320 input->src.dcc = pipe->plane_state->dcc.enable ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
330 input->src.dcc = pipe->plane_res.dpp->ctx->dc->res_pool->hubbub->funcs-> in pipe_ctx_to_e2e_pipe_params()
331 dcc_support_pixel_format(pipe->plane_state->format, &bpe) ? 1 : 0; in pipe_ctx_to_e2e_pipe_params()
334 input->src.meta_pitch = pipe->plane_state->dcc.meta_pitch; in pipe_ctx_to_e2e_pipe_params()
336 input->src.sw_mode = pipe->plane_state->tiling_info.gfx9.swizzle; in pipe_ctx_to_e2e_pipe_params()
338 input->src.viewport_width = pipe->plane_res.scl_data.viewport.width; in pipe_ctx_to_e2e_pipe_params()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/i915/gvt/
H A Ddisplay.c46 int pipe = -1; in get_edp_pipe() local
51 pipe = PIPE_A; in get_edp_pipe()
54 pipe = PIPE_B; in get_edp_pipe()
57 pipe = PIPE_C; in get_edp_pipe()
60 return pipe; in get_edp_pipe()
75 int pipe_is_enabled(struct intel_vgpu *vgpu, int pipe) in pipe_is_enabled() argument
79 if (WARN_ON(pipe < PIPE_A || pipe >= I915_MAX_PIPES)) in pipe_is_enabled()
82 if (vgpu_vreg_t(vgpu, PIPECONF(pipe)) & PIPECONF_ENABLE) in pipe_is_enabled()
86 get_edp_pipe(vgpu) == pipe) in pipe_is_enabled()
177 int pipe; in emulate_monitor_status_change() local
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H A Dfb_decoder.c151 static u32 intel_vgpu_get_stride(struct intel_vgpu *vgpu, int pipe, in intel_vgpu_get_stride() argument
156 u32 stride_reg = vgpu_vreg_t(vgpu, DSPSTRIDE(pipe)) & stride_mask; in intel_vgpu_get_stride()
212 int pipe; in intel_vgpu_decode_primary_plane() local
214 pipe = get_active_pipe(vgpu); in intel_vgpu_decode_primary_plane()
215 if (pipe >= I915_MAX_PIPES) in intel_vgpu_decode_primary_plane()
218 val = vgpu_vreg_t(vgpu, DSPCNTR(pipe)); in intel_vgpu_decode_primary_plane()
252 plane->base = vgpu_vreg_t(vgpu, DSPSURF(pipe)) & I915_GTT_PAGE_MASK; in intel_vgpu_decode_primary_plane()
263 plane->stride = intel_vgpu_get_stride(vgpu, pipe, plane->tiled, in intel_vgpu_decode_primary_plane()
268 plane->width = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & _PIPE_H_SRCSZ_MASK) >> in intel_vgpu_decode_primary_plane()
271 plane->height = (vgpu_vreg_t(vgpu, PIPESRC(pipe)) & in intel_vgpu_decode_primary_plane()
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/netbsd-src/external/mit/libuv/dist/test/
H A Dtest-getters-setters.c56 uv_pipe_t* pipe; in TEST_IMPL() local
69 pipe = malloc(uv_handle_size(UV_NAMED_PIPE)); in TEST_IMPL()
70 r = uv_pipe_init(loop, pipe, 0); in TEST_IMPL()
71 ASSERT(uv_handle_get_type((uv_handle_t*)pipe) == UV_NAMED_PIPE); in TEST_IMPL()
73 ASSERT(uv_handle_get_loop((uv_handle_t*)pipe) == loop); in TEST_IMPL()
74 pipe->data = &cookie2; in TEST_IMPL()
75 ASSERT(uv_handle_get_data((uv_handle_t*)pipe) == &cookie2); in TEST_IMPL()
76 uv_handle_set_data((uv_handle_t*)pipe, &cookie1); in TEST_IMPL()
77 ASSERT(uv_handle_get_data((uv_handle_t*)pipe) == &cookie1); in TEST_IMPL()
78 ASSERT(pipe->data == &cookie1); in TEST_IMPL()
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/netbsd-src/sys/external/bsd/drm/dist/shared-core/
H A Di915_irq.c78 i915_pipestat(unsigned int pipe) in i915_pipestat() argument
80 if (pipe == 0) in i915_pipestat()
82 if (pipe == 1) in i915_pipestat()
88 i915_enable_pipestat(drm_i915_private_t *dev_priv, unsigned int pipe, u32 mask) in i915_enable_pipestat() argument
90 if ((dev_priv->pipestat[pipe] & mask) != mask) { in i915_enable_pipestat()
91 u32 reg = i915_pipestat(pipe); in i915_enable_pipestat()
93 dev_priv->pipestat[pipe] |= mask; in i915_enable_pipestat()
95 I915_WRITE(reg, dev_priv->pipestat[pipe] | (mask >> 16)); in i915_enable_pipestat()
101 i915_disable_pipestat(drm_i915_private_t *dev_priv, unsigned int pipe, u32 mask) in i915_disable_pipestat() argument
103 if ((dev_priv->pipestat[pipe] & mask) != 0) { in i915_disable_pipestat()
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/netbsd-src/external/mit/libuv/dist/src/win/
H A Dpipe.c93 static void eof_timer_init(uv_pipe_t* pipe);
94 static void eof_timer_start(uv_pipe_t* pipe);
95 static void eof_timer_stop(uv_pipe_t* pipe);
97 static void eof_timer_destroy(uv_pipe_t* pipe);
112 handle->pipe.conn.ipc_remote_pid = 0; in uv_pipe_init()
113 handle->pipe.conn.ipc_data_frame.payload_remaining = 0; in uv_pipe_init()
114 QUEUE_INIT(&handle->pipe.conn.ipc_xfer_queue); in uv_pipe_init()
115 handle->pipe.conn.ipc_xfer_queue_length = 0; in uv_pipe_init()
117 handle->pipe.conn.non_overlapped_writes_tail = NULL; in uv_pipe_init()
127 handle->pipe.conn.eof_timer = NULL; in uv__pipe_connection_init()
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/netbsd-src/sys/external/bsd/drm2/dist/drm/xen/
H A Dxen_drm_front_kms.c36 to_xen_drm_pipeline(struct drm_simple_display_pipe *pipe) in to_xen_drm_pipeline() argument
38 return container_of(pipe, struct xen_drm_front_drm_pipeline, pipe); in to_xen_drm_pipeline()
98 struct drm_crtc *crtc = &pipeline->pipe.crtc; in send_pending_event()
109 static void display_enable(struct drm_simple_display_pipe *pipe, in display_enable() argument
114 to_xen_drm_pipeline(pipe); in display_enable()
115 struct drm_crtc *crtc = &pipe->crtc; in display_enable()
119 if (!drm_dev_enter(pipe->crtc.dev, &idx)) in display_enable()
135 static void display_disable(struct drm_simple_display_pipe *pipe) in display_disable() argument
138 to_xen_drm_pipeline(pipe); in display_disable()
141 if (drm_dev_enter(pipe->crtc.dev, &idx)) { in display_disable()
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/netbsd-src/sys/dev/pci/igma/
H A Digmafb.c382 int pipe = cd->use_pipe; in igmafb_guess_size() local
385 r = co->read_reg(cd, PIPE_HTOTAL(pipe)); in igmafb_guess_size()
387 r = co->read_reg(cd, PIPE_VTOTAL(pipe)); in igmafb_guess_size()
395 r = co->read_reg(cd, PF_WINSZ(pipe)); in igmafb_guess_size()
413 int pipe = cd->use_pipe; in igmafb_set_mode() local
431 co->write_reg(cd, PF_WINPOS(pipe), in igmafb_set_mode()
433 co->write_reg(cd, PF_WINSZ(pipe), in igmafb_set_mode()
437 co->write_reg(cd, PIPE_SRCSZ(pipe), in igmafb_set_mode()
441 co->write_reg(cd, PIPE_CONF(pipe), in igmafb_set_mode()
445 r = co->read_reg(cd, PRI_CTRL(pipe)); in igmafb_set_mode()
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