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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-objdump/
H A DMachODump.cpp239 dumpBytes(makeArrayRef(bytes, 4), outs()); in DumpDataInCode()
241 outs() << "\t.long " << Value; in DumpDataInCode()
245 dumpBytes(makeArrayRef(bytes, 2), outs()); in DumpDataInCode()
247 outs() << "\t.short " << Value; in DumpDataInCode()
251 dumpBytes(makeArrayRef(bytes, 2), outs()); in DumpDataInCode()
253 outs() << "\t.byte " << Value; in DumpDataInCode()
257 outs() << "\t@ KIND_DATA\n"; in DumpDataInCode()
259 outs() << "\t@ data in code kind = " << Kind << "\n"; in DumpDataInCode()
263 dumpBytes(makeArrayRef(bytes, 1), outs()); in DumpDataInCode()
265 outs() << "\t.byte " << format("%3u", Value) << "\t@ KIND_JUMP_TABLE8\n"; in DumpDataInCode()
[all …]
H A DCOFFDump.cpp98 outs() << format(" 0x%02x: ", unsigned(UCs[0].u.CodeOffset)) in printUnwindCode()
102 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()); in printUnwindCode()
106 outs() << " " << UCs[1].FrameOffset; in printUnwindCode()
108 outs() << " " << UCs[1].FrameOffset in printUnwindCode()
113 outs() << " " << ((UCs[0].getOpInfo() + 1) * 8); in printUnwindCode()
116 outs() << " "; in printUnwindCode()
119 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()) in printUnwindCode()
123 outs() << " " << getUnwindRegisterName(UCs[0].getOpInfo()) in printUnwindCode()
128 outs() << " XMM" << static_cast<uint32_t>(UCs[0].getOpInfo()) in printUnwindCode()
132 outs() << " XMM" << UCs[0].getOpInfo() in printUnwindCode()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyInstrConv.td15 defm I32_WRAP_I64 : I<(outs I32:$dst), (ins I64:$src), (outs), (ins),
19 defm I64_EXTEND_S_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
23 defm I64_EXTEND_U_I32 : I<(outs I64:$dst), (ins I32:$src), (outs), (ins),
29 defm I32_EXTEND8_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
33 defm I32_EXTEND16_S_I32 : I<(outs I32:$dst), (ins I32:$src), (outs), (ins),
37 defm I64_EXTEND8_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
41 defm I64_EXTEND16_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
45 defm I64_EXTEND32_S_I64 : I<(outs I64:$dst), (ins I64:$src), (outs), (ins),
58 defm I32_TRUNC_S_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
63 defm I32_TRUNC_U_SAT_F32 : I<(outs I32:$dst), (ins F32:$src), (outs), (ins),
[all …]
H A DWebAssemblyInstrControl.td16 defm BR_IF : I<(outs), (ins bb_op:$dst, I32:$cond),
17 (outs), (ins bb_op:$dst),
21 defm BR_UNLESS : I<(outs), (ins bb_op:$dst, I32:$cond),
22 (outs), (ins bb_op:$dst), []>;
24 defm BR : NRI<(outs), (ins bb_op:$dst),
50 defm BR_TABLE_I32 : I<(outs), (ins I32:$index, variable_ops),
51 (outs), (ins brlist:$brl),
58 defm BR_TABLE_I64 : I<(outs), (ins I64:$index, variable_ops),
59 (outs), (ins brlist:$brl),
67 defm NOP : NRI<(outs), (ins), [], "nop", 0x01>;
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrSPE.td140 def BRINC : EVXForm_1<527, (outs gprc:$RT), (ins gprc:$RA, gprc:$RB),
144 def EFDABS : EFXForm_2<740, (outs sperc:$RT), (ins sperc:$RA),
148 def EFDADD : EFXForm_1<736, (outs sperc:$RT), (ins sperc:$RA, sperc:$RB),
152 def EFDCFS : EFXForm_2a<751, (outs sperc:$RT), (ins spe4rc:$RB),
156 def EFDCFSF : EFXForm_2a<755, (outs sperc:$RT), (ins spe4rc:$RB),
159 def EFDCFSI : EFXForm_2a<753, (outs sperc:$RT), (ins gprc:$RB),
163 def EFDCFSID : EFXForm_2a<739, (outs sperc:$RT), (ins gprc:$RB),
167 def EFDCFUF : EFXForm_2a<754, (outs sperc:$RT), (ins spe4rc:$RB),
170 def EFDCFUI : EFXForm_2a<752, (outs sperc:$RT), (ins gprc:$RB),
174 def EFDCFUID : EFXForm_2a<738, (outs sperc:$RT), (ins gprc:$RB),
[all …]
H A DPPCInstr64Bit.td78 def BLR8 : XLForm_2_ext<19, 16, 20, 0, 0, (outs), (ins), "blr", IIC_BrB,
82 def BCTR8 : XLForm_2_ext<19, 528, 20, 0, 0, (outs), (ins), "bctr", IIC_BrB,
85 def BCCCTR8 : XLForm_2_br<19, 528, 0, (outs), (ins pred:$cond),
90 def BCCTR8 : XLForm_2_br2<19, 528, 12, 0, (outs), (ins crbitrc:$bi),
93 def BCCTR8n : XLForm_2_br2<19, 528, 4, 0, (outs), (ins crbitrc:$bi),
100 def MovePCtoLR8 : PPCEmitTimePseudo<(outs), (ins), "#MovePCtoLR8", []>,
105 def BDZ8 : BForm_1<16, 18, 0, 0, (outs), (ins condbrtarget:$dst),
107 def BDNZ8 : BForm_1<16, 16, 0, 0, (outs), (ins condbrtarget:$dst),
112 def BDZLR8 : XLForm_2_ext<19, 16, 18, 0, 0, (outs), (ins),
114 def BDNZLR8 : XLForm_2_ext<19, 16, 16, 0, 0, (outs), (ins),
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/
H A DMSP430InstrFormats.td32 class MSP430Inst<dag outs, dag ins, int size, string asmstr> : Instruction {
38 dag OutOperandList = outs;
47 dag outs, dag ins, string asmstr, list<dag> pattern>
48 : MSP430Inst<outs, ins, size, asmstr> {
64 dag outs, dag ins, string asmstr, list<dag> pattern>
65 : IForm<opcode, dest, 1, src, size, outs, ins, asmstr, pattern>;
68 dag outs, dag ins, string asmstr, list<dag> pattern>
69 : IForm8<opcode, DstReg, SrcReg, 2, outs, ins, asmstr, pattern> {
74 dag outs, dag ins, string asmstr, list<dag> pattern>
75 : IForm8<opcode, DstReg, SrcImm, 4, outs, ins, asmstr, pattern> {
[all …]
H A DMSP430InstrInfo.td174 def ADJCALLSTACKDOWN : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
177 def ADJCALLSTACKUP : Pseudo<(outs), (ins i16imm:$amt1, i16imm:$amt2),
183 def ADDframe : Pseudo<(outs GR16:$dst), (ins i16imm:$base, i16imm:$offset),
189 def Select8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$src2, i8imm:$cc),
193 def Select16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR16:$src2, i8imm:$cc),
199 def Shl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
202 def Shl16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
205 def Sra8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
208 def Sra16 : Pseudo<(outs GR16:$dst), (ins GR16:$src, GR8:$cnt),
211 def Srl8 : Pseudo<(outs GR8:$dst), (ins GR8:$src, GR8:$cnt),
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstrSystem.td17 def RDTSC : I<0x31, RawFrm, (outs), (ins), "rdtsc", []>, TB;
20 def RDTSCP : I<0x01, MRM_F9, (outs), (ins), "rdtscp", []>, TB;
25 def TRAP : I<0x0B, RawFrm, (outs), (ins), "ud2", [(trap)]>, TB;
27 def UD1Wm : I<0xB9, MRMSrcMem, (outs), (ins GR16:$src1, i16mem:$src2),
29 def UD1Lm : I<0xB9, MRMSrcMem, (outs), (ins GR32:$src1, i32mem:$src2),
31 def UD1Qm : RI<0xB9, MRMSrcMem, (outs), (ins GR64:$src1, i64mem:$src2),
34 def UD1Wr : I<0xB9, MRMSrcReg, (outs), (ins GR16:$src1, GR16:$src2),
36 def UD1Lr : I<0xB9, MRMSrcReg, (outs), (ins GR32:$src1, GR32:$src2),
38 def UD1Qr : RI<0xB9, MRMSrcReg, (outs), (ins GR64:$src1, GR64:$src2),
42 def HLT : I<0xF4, RawFrm, (outs), (ins), "hlt", []>;
[all …]
H A DX86InstrFPStack.td126 def FP32_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP32:$src),
128 def FP32_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP32:$src),
130 def FP32_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP32:$src),
132 def FP64_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP64:$src),
134 def FP64_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP64:$src),
136 def FP64_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP64:$src),
138 def FP80_TO_INT16_IN_MEM : PseudoI<(outs), (ins i16mem:$dst, RFP80:$src),
140 def FP80_TO_INT32_IN_MEM : PseudoI<(outs), (ins i32mem:$dst, RFP80:$src),
142 def FP80_TO_INT64_IN_MEM : PseudoI<(outs), (ins i64mem:$dst, RFP80:$src),
169 class FpIf32<dag outs, dag ins, FPFormat fp, list<dag> pattern> :
[all …]
H A DX86InstrControl.td23 def RETL : I <0xC3, RawFrm, (outs), (ins variable_ops),
25 def RETQ : I <0xC3, RawFrm, (outs), (ins variable_ops),
27 def RETW : I <0xC3, RawFrm, (outs), (ins),
29 def RETIL : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
31 def RETIQ : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt, variable_ops),
33 def RETIW : Ii16<0xC2, RawFrm, (outs), (ins i16imm:$amt),
35 def LRETL : I <0xCB, RawFrm, (outs), (ins),
37 def LRETQ : RI <0xCB, RawFrm, (outs), (ins),
39 def LRETW : I <0xCB, RawFrm, (outs), (ins),
41 def LRETIL : Ii16<0xCA, RawFrm, (outs), (ins i16imm:$amt),
[all …]
H A DX86InstrFormats.td270 class X86Inst<bits<8> opcod, Format f, ImmType i, dag outs, dag ins,
280 dag OutOperandList = outs;
392 class I<bits<8> o, Format f, dag outs, dag ins, string asm,
394 : X86Inst<o, f, NoImm, outs, ins, asm, d> {
398 class Ii8<bits<8> o, Format f, dag outs, dag ins, string asm,
400 : X86Inst<o, f, Imm8, outs, ins, asm, d> {
404 class Ii8Reg<bits<8> o, Format f, dag outs, dag ins, string asm,
406 : X86Inst<o, f, Imm8Reg, outs, ins, asm, d> {
410 class Ii8PCRel<bits<8> o, Format f, dag outs, dag ins, string asm,
412 : X86Inst<o, f, Imm8PCRel, outs, ins, asm> {
[all …]
H A DX86InstrShiftRotate.td19 def SHL8rCL : I<0xD2, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1),
22 def SHL16rCL : I<0xD3, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
25 def SHL32rCL : I<0xD3, MRM4r, (outs GR32:$dst), (ins GR32:$src1),
28 def SHL64rCL : RI<0xD3, MRM4r, (outs GR64:$dst), (ins GR64:$src1),
34 def SHL8ri : Ii8<0xC0, MRM4r, (outs GR8 :$dst), (ins GR8 :$src1, u8imm:$src2),
38 def SHL16ri : Ii8<0xC1, MRM4r, (outs GR16:$dst), (ins GR16:$src1, u8imm:$src2),
42 def SHL32ri : Ii8<0xC1, MRM4r, (outs GR32:$dst), (ins GR32:$src1, u8imm:$src2),
46 def SHL64ri : RIi8<0xC1, MRM4r, (outs GR64:$dst),
55 def SHL8r1 : I<0xD0, MRM4r, (outs GR8:$dst), (ins GR8:$src1),
57 def SHL16r1 : I<0xD1, MRM4r, (outs GR16:$dst), (ins GR16:$src1),
[all …]
H A DX86InstrVMX.td19 def INVEPT32 : I<0x80, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
22 def INVEPT64 : I<0x80, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
27 def INVVPID32 : I<0x81, MRMSrcMem, (outs), (ins GR32:$src1, i128mem:$src2),
30 def INVVPID64 : I<0x81, MRMSrcMem, (outs), (ins GR64:$src1, i128mem:$src2),
35 def VMCALL : I<0x01, MRM_C1, (outs), (ins), "vmcall", []>, TB;
36 def VMCLEARm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
40 def VMFUNC : I<0x01, MRM_D4, (outs), (ins), "vmfunc", []>, PS;
43 def VMLAUNCH : I<0x01, MRM_C2, (outs), (ins), "vmlaunch", []>, TB;
46 def VMRESUME : I<0x01, MRM_C3, (outs), (ins), "vmresume", []>, TB;
47 def VMPTRLDm : I<0xC7, MRM6m, (outs), (ins i64mem:$vmcs),
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreInstrFormats.td12 class InstXCore<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
17 dag OutOperandList = outs;
26 class PseudoInstXCore<dag outs, dag ins, string asmstr, list<dag> pattern>
27 : InstXCore<0, outs, ins, asmstr, pattern> {
35 class _F3R<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
36 : InstXCore<2, outs, ins, asmstr, pattern> {
44 class _F3RImm<bits<5> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
45 : _F3R<opc, outs, ins, asmstr, pattern> {
49 class _FL3R<bits<9> opc, dag outs, dag ins, string asmstr, list<dag> pattern>
50 : InstXCore<4, outs, ins, asmstr, pattern> {
[all …]
H A DXCoreInstrInfo.td214 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
217 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
223 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
225 def _2rus : _F2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
231 def _3r: _F3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
234 def _2rus : _F2RUSBitp<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
240 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
245 _F3R<opc, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
252 def _l3r: _FL3R<opc1, (outs GRRegs:$dst), (ins GRRegs:$b, GRRegs:$c),
255 def _l2rus : _FL2RUS<opc2, (outs GRRegs:$dst), (ins GRRegs:$b, i32imm:$c),
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/netbsd-src/external/apache2/llvm/dist/llvm/examples/OrcV2Examples/LLJITWithObjectLinkingLayerPlugin/
H A DLLJITWithObjectLinkingLayerPlugin.cpp59 outs() << "MyPlugin -- Modifying pass config for " << LG.getName() << " (" in modifyPassConfig()
74 outs() << "Loading object defining " << MR.getSymbols() << "\n"; in notifyLoaded()
78 outs() << "Emitted object defining " << MR.getSymbols() << "\n"; in notifyEmitted()
98 outs() << " " << formatv("{0:x16}", B.getAddress()) << ": " in printBlockContent()
110 outs() << " " << formatv("{0:x16}", CurAddr) << ": "; in printBlockContent()
112 outs() << " "; in printBlockContent()
114 outs() << formatv("{0:x-2}", Data[CurAddr - StartAddr]) << " "; in printBlockContent()
116 outs() << "\n"; in printBlockContent()
119 outs() << "\n"; in printBlockContent()
126 outs() << "Graph \"" << G.getName() << "\"\n"; in printGraph()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/tools/bugpoint/
H A DFindBugs.cpp25 outs() << "Starting bug finding procedure...\n\n"; in runManyPasses()
31 outs() << "\n"; in runManyPasses()
33 outs() << "Generating reference output from raw program: \n"; in runManyPasses()
49 outs() << "Running selected passes on program to test for crash: "; in runManyPasses()
51 outs() << "-" << PassesToRun[i] << " "; in runManyPasses()
56 outs() << "\n"; in runManyPasses()
57 outs() << "Optimizer passes caused failure!\n\n"; in runManyPasses()
60 outs() << "Combination " << num << " optimized successfully!\n"; in runManyPasses()
66 outs() << "Running the code generator to test for a crash: "; in runManyPasses()
68 outs() << "\n*** compileProgram threw an exception: "; in runManyPasses()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrFormats.td9 class InstSP<dag outs, dag ins, string asmstr, list<dag> pattern,
20 dag OutOperandList = outs;
36 class F2<dag outs, dag ins, string asmstr, list<dag> pattern,
38 : InstSP<outs, ins, asmstr, pattern, itin> {
48 class F2_1<bits<3> op2Val, dag outs, dag ins, string asmstr, list<dag> pattern,
50 : F2<outs, ins, asmstr, pattern, itin> {
58 class F2_2<bits<3> op2Val, bit annul, dag outs, dag ins, string asmstr,
60 : F2<outs, ins, asmstr, pattern, itin> {
69 dag outs, dag ins, string asmstr, list<dag> pattern,
71 : InstSP<outs, ins, asmstr, pattern, itin> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Target/
H A DGenericOpcodes.td41 let OutOperandList = (outs type0:$dst);
49 let OutOperandList = (outs type0:$dst);
63 let OutOperandList = (outs type0:$dst);
71 let OutOperandList = (outs type0:$dst);
80 let OutOperandList = (outs type0:$dst);
86 let OutOperandList = (outs type0:$dst);
92 let OutOperandList = (outs type0:$dst);
98 let OutOperandList = (outs type0:$dst);
104 let OutOperandList = (outs type0:$dst);
110 let OutOperandList = (outs type0:$dst);
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRInstrFormats.td14 class AVRInst<dag outs, dag ins, string asmstr, list<dag> pattern> : Instruction
18 dag OutOperandList = outs;
27 class AVRInst16<dag outs, dag ins, string asmstr, list<dag> pattern>
28 : AVRInst<outs, ins, asmstr, pattern>
36 class AVRInst32<dag outs, dag ins, string asmstr, list<dag> pattern>
37 : AVRInst<outs, ins, asmstr, pattern>
52 class Pseudo<dag outs, dag ins, string asmstr, list<dag> pattern>
53 : AVRInst16<outs, ins, asmstr, pattern>
69 class FRdRr<bits<4> opcode, bits<2> f, dag outs, dag ins, string asmstr,
70 list<dag> pattern> : AVRInst16<outs, ins, asmstr, pattern>
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCInstrFormats.td96 class InstARC<int sz, dag outs, dag ins, string asmstr, list<dag> pattern>
100 dag OutOperandList = outs;
120 class PseudoInstARC<dag outs, dag ins, string asmstr, list<dag> pattern>
121 : InstARC<0, outs, ins, asmstr, pattern> {
155 class F32_BR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
157 InstARC<4, outs, ins, asmstr, pattern> {
165 class F32_BR_COND<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
167 F32_BR<major, outs, ins, b16, asmstr, pattern> {
175 class F32_BR_UCOND_FAR<bits<5> major, dag outs, dag ins, bit b16, string asmstr,
177 F32_BR<major, outs, ins, b16, asmstr, pattern> {
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/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-size/
H A Dllvm-size.cpp231 outs() << "Segment " << Seg.segname << ": " in printDarwinSectionSizes()
234 outs() << " (vmaddr 0x" << format("%" PRIx64, Seg.vmaddr) << " fileoff " in printDarwinSectionSizes()
236 outs() << "\n"; in printDarwinSectionSizes()
242 outs() << "\tSection (" << format("%.16s", &Sec.segname) << ", " in printDarwinSectionSizes()
245 outs() << "\tSection " << format("%.16s", &Sec.sectname) << ": "; in printDarwinSectionSizes()
246 outs() << format(fmt.str().c_str(), Sec.size); in printDarwinSectionSizes()
248 outs() << " (addr 0x" << format("%" PRIx64, Sec.addr) << " offset " in printDarwinSectionSizes()
250 outs() << "\n"; in printDarwinSectionSizes()
254 outs() << "\ttotal " << format(fmt.str().c_str(), sec_total) << "\n"; in printDarwinSectionSizes()
258 outs() << "Segment " << Seg.segname << ": " in printDarwinSectionSizes()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMips16InstrFormats.td35 class MipsInst16_Base<dag outs, dag ins, string asmstr, list<dag> pattern,
41 let OutOperandList = outs;
54 class MipsInst16<dag outs, dag ins, string asmstr, list<dag> pattern,
56 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
71 class MipsInst16_32<dag outs, dag ins, string asmstr, list<dag> pattern,
73 MipsInst16_Base<outs, ins, asmstr, pattern, itin>
81 class MipsInst16_EXTEND<dag outs, dag ins, string asmstr, list<dag> pattern,
83 MipsInst16_32<outs, ins, asmstr, pattern, itin>
91 class MipsPseudo16<dag outs, dag ins, string asmstr, list<dag> pattern>:
92 MipsInst16<outs, ins, asmstr, pattern, IIPseudo> {
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/tools/llvm-cxxdump/
H A Dllvm-cxxdump.cpp46 WithColor::error(outs(), "") << "reading file: " << EC.message() << ".\n"; in error()
47 outs().flush(); in error()
52 logAllUnhandledErrors(std::move(Err), WithColor::error(outs()), in error()
54 outs().flush(); in error()
347 outs() << VFTableName << '[' << Offset << "]: " << SymName << '\n'; in dumpCXXData()
353 outs() << VBTableName << '[' << Idx << "]: " << Offset << '\n'; in dumpCXXData()
360 outs() << COLName << "[IsImageRelative]: " << COL.Data[0] << '\n'; in dumpCXXData()
361 outs() << COLName << "[OffsetToTop]: " << COL.Data[1] << '\n'; in dumpCXXData()
362 outs() << COLName << "[VFPtrOffset]: " << COL.Data[2] << '\n'; in dumpCXXData()
363 outs() << COLName << "[TypeDescriptor]: " << COL.Symbols[0] << '\n'; in dumpCXXData()
[all …]

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