Home
last modified time | relevance | path

Searched refs:out_reg (Results 1 – 21 of 21) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/powerplay/smumgr/
H A Damdgpu_iceland_smumgr.c2379 static bool iceland_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg) in iceland_check_s0_mc_reg_index() argument
2385 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in iceland_check_s0_mc_reg_index()
2389 *out_reg = mmMC_SEQ_DLL_STBY_LP; in iceland_check_s0_mc_reg_index()
2393 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; in iceland_check_s0_mc_reg_index()
2397 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; in iceland_check_s0_mc_reg_index()
2401 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; in iceland_check_s0_mc_reg_index()
2405 *out_reg = mmMC_SEQ_CAS_TIMING_LP; in iceland_check_s0_mc_reg_index()
2409 *out_reg = mmMC_SEQ_MISC_TIMING_LP; in iceland_check_s0_mc_reg_index()
2413 *out_reg = mmMC_SEQ_MISC_TIMING2_LP; in iceland_check_s0_mc_reg_index()
2417 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP; in iceland_check_s0_mc_reg_index()
[all …]
H A Damdgpu_ci_smumgr.c2450 static bool ci_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg) in ci_check_s0_mc_reg_index() argument
2456 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in ci_check_s0_mc_reg_index()
2460 *out_reg = mmMC_SEQ_DLL_STBY_LP; in ci_check_s0_mc_reg_index()
2464 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; in ci_check_s0_mc_reg_index()
2468 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; in ci_check_s0_mc_reg_index()
2472 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; in ci_check_s0_mc_reg_index()
2476 *out_reg = mmMC_SEQ_CAS_TIMING_LP; in ci_check_s0_mc_reg_index()
2480 *out_reg = mmMC_SEQ_MISC_TIMING_LP; in ci_check_s0_mc_reg_index()
2484 *out_reg = mmMC_SEQ_MISC_TIMING2_LP; in ci_check_s0_mc_reg_index()
2488 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP; in ci_check_s0_mc_reg_index()
[all …]
H A Damdgpu_tonga_smumgr.c2840 static bool tonga_check_s0_mc_reg_index(uint16_t in_reg, uint16_t *out_reg) in tonga_check_s0_mc_reg_index() argument
2846 *out_reg = mmMC_SEQ_RAS_TIMING_LP; in tonga_check_s0_mc_reg_index()
2850 *out_reg = mmMC_SEQ_DLL_STBY_LP; in tonga_check_s0_mc_reg_index()
2854 *out_reg = mmMC_SEQ_G5PDX_CMD0_LP; in tonga_check_s0_mc_reg_index()
2858 *out_reg = mmMC_SEQ_G5PDX_CMD1_LP; in tonga_check_s0_mc_reg_index()
2862 *out_reg = mmMC_SEQ_G5PDX_CTRL_LP; in tonga_check_s0_mc_reg_index()
2866 *out_reg = mmMC_SEQ_CAS_TIMING_LP; in tonga_check_s0_mc_reg_index()
2870 *out_reg = mmMC_SEQ_MISC_TIMING_LP; in tonga_check_s0_mc_reg_index()
2874 *out_reg = mmMC_SEQ_MISC_TIMING2_LP; in tonga_check_s0_mc_reg_index()
2878 *out_reg = mmMC_SEQ_PMG_DVS_CMD_LP; in tonga_check_s0_mc_reg_index()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_btc_dpm.c1860 static bool btc_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) in btc_check_s0_mc_reg_index() argument
1866 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
1869 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
1872 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in btc_check_s0_mc_reg_index()
1875 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in btc_check_s0_mc_reg_index()
1878 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; in btc_check_s0_mc_reg_index()
1881 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; in btc_check_s0_mc_reg_index()
1884 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in btc_check_s0_mc_reg_index()
1887 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in btc_check_s0_mc_reg_index()
1890 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in btc_check_s0_mc_reg_index()
[all …]
H A Dradeon_ci_dpm.c4413 static bool ci_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) in ci_check_s0_mc_reg_index() argument
4419 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4422 *out_reg = MC_SEQ_DLL_STBY_LP >> 2; in ci_check_s0_mc_reg_index()
4425 *out_reg = MC_SEQ_G5PDX_CMD0_LP >> 2; in ci_check_s0_mc_reg_index()
4428 *out_reg = MC_SEQ_G5PDX_CMD1_LP >> 2; in ci_check_s0_mc_reg_index()
4431 *out_reg = MC_SEQ_G5PDX_CTRL_LP >> 2; in ci_check_s0_mc_reg_index()
4434 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4437 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in ci_check_s0_mc_reg_index()
4440 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in ci_check_s0_mc_reg_index()
4443 *out_reg = MC_SEQ_PMG_DVS_CMD_LP >> 2; in ci_check_s0_mc_reg_index()
[all …]
H A Dradeon_ni_dpm.c2772 static bool ni_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) in ni_check_s0_mc_reg_index() argument
2778 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2781 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2784 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in ni_check_s0_mc_reg_index()
2787 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in ni_check_s0_mc_reg_index()
2790 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; in ni_check_s0_mc_reg_index()
2793 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; in ni_check_s0_mc_reg_index()
2796 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in ni_check_s0_mc_reg_index()
2799 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in ni_check_s0_mc_reg_index()
2802 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in ni_check_s0_mc_reg_index()
[all …]
H A Dradeon_si_dpm.c5429 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) in si_check_s0_mc_reg_index() argument
5435 *out_reg = MC_SEQ_RAS_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5438 *out_reg = MC_SEQ_CAS_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5441 *out_reg = MC_SEQ_MISC_TIMING_LP >> 2; in si_check_s0_mc_reg_index()
5444 *out_reg = MC_SEQ_MISC_TIMING2_LP >> 2; in si_check_s0_mc_reg_index()
5447 *out_reg = MC_SEQ_RD_CTL_D0_LP >> 2; in si_check_s0_mc_reg_index()
5450 *out_reg = MC_SEQ_RD_CTL_D1_LP >> 2; in si_check_s0_mc_reg_index()
5453 *out_reg = MC_SEQ_WR_CTL_D0_LP >> 2; in si_check_s0_mc_reg_index()
5456 *out_reg = MC_SEQ_WR_CTL_D1_LP >> 2; in si_check_s0_mc_reg_index()
5459 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP >> 2; in si_check_s0_mc_reg_index()
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/
H A Dreload1.cc5901 || (out && rld[reloadnum].out_reg in reload_reg_free_for_value_p()
6975 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) in choose_reload_regs()
6978 int nregno = REGNO (rld[r].out_reg); in choose_reload_regs()
7131 rl->out_reg))) in emit_input_reload_insns()
7180 if (rl->out && ! rl->out_reg) in emit_input_reload_insns()
7720 rld[s].out_reg = rl->out_reg; in emit_output_reload_insns()
7811 && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) in do_input_reload()
7845 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg))) in do_input_reload()
7861 rtx pseudo = rl->out_reg; in do_output_reload()
7907 old = rl->out_reg; in do_output_reload()
[all …]
H A Dreload.h106 rtx out_reg; member
H A DChangeLog-200811621 * reload.c (push_reload): Merge in,out,in_reg,out_reg members
/netbsd-src/external/gpl3/gcc.old/dist/gcc/
H A Dreload1.c5905 || (out && rld[reloadnum].out_reg in reload_reg_free_for_value_p()
6979 if (rld[r].out_reg != 0 && REG_P (rld[r].out_reg) in choose_reload_regs()
6982 int nregno = REGNO (rld[r].out_reg); in choose_reload_regs()
7135 rl->out_reg))) in emit_input_reload_insns()
7184 if (rl->out && ! rl->out_reg) in emit_input_reload_insns()
7724 rld[s].out_reg = rl->out_reg; in emit_output_reload_insns()
7815 && (! reload_inherited[j] || (rl->out && ! rl->out_reg)) in do_input_reload()
7849 || rtx_equal_p (spill_reg_stored_to[REGNO (reg_rtx)], rl->out_reg))) in do_input_reload()
7865 rtx pseudo = rl->out_reg; in do_output_reload()
7911 old = rl->out_reg; in do_output_reload()
[all …]
H A Dreload.h106 rtx out_reg; member
H A Dreload.c483 rld[s_reload].out_reg = 0; in push_secondary_reload()
1389 rld[i].out_reg = outloc ? *outloc : 0; in push_reload()
1479 && (!rld[i].out_reg in push_reload()
1480 || partial_subreg_p (GET_MODE (rld[i].out_reg), in push_reload()
1482 rld[i].out_reg = *outloc; in push_reload()
1846 rld[i].out_reg = rld[output_reload].out_reg; in combine_reloads()
7371 if (rld[r].out_reg != 0) in debug_reload_to_stream()
7374 print_inline_rtx (f, rld[r].out_reg, 24); in debug_reload_to_stream()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_si_dpm.c5886 static bool si_check_s0_mc_reg_index(u16 in_reg, u16 *out_reg) in si_check_s0_mc_reg_index() argument
5891 *out_reg = MC_SEQ_RAS_TIMING_LP; in si_check_s0_mc_reg_index()
5894 *out_reg = MC_SEQ_CAS_TIMING_LP; in si_check_s0_mc_reg_index()
5897 *out_reg = MC_SEQ_MISC_TIMING_LP; in si_check_s0_mc_reg_index()
5900 *out_reg = MC_SEQ_MISC_TIMING2_LP; in si_check_s0_mc_reg_index()
5903 *out_reg = MC_SEQ_RD_CTL_D0_LP; in si_check_s0_mc_reg_index()
5906 *out_reg = MC_SEQ_RD_CTL_D1_LP; in si_check_s0_mc_reg_index()
5909 *out_reg = MC_SEQ_WR_CTL_D0_LP; in si_check_s0_mc_reg_index()
5912 *out_reg = MC_SEQ_WR_CTL_D1_LP; in si_check_s0_mc_reg_index()
5915 *out_reg = MC_SEQ_PMG_CMD_EMRS_LP; in si_check_s0_mc_reg_index()
[all …]
/netbsd-src/sys/dev/pci/ixgbe/
H A Dixgbe_common.h174 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg);
H A Dixgbe_api.c1393 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg) in ixgbe_bypass_valid_rd() argument
1396 (in_reg, out_reg), IXGBE_NOT_IMPLEMENTED); in ixgbe_bypass_valid_rd()
H A Dixgbe_api.h206 bool ixgbe_bypass_valid_rd(struct ixgbe_hw *hw, u32 in_reg, u32 out_reg);
H A Dixgbe_common.c5054 bool ixgbe_bypass_valid_rd_generic(u32 in_reg, u32 out_reg) in ixgbe_bypass_valid_rd_generic() argument
5059 if ((in_reg & BYPASS_PAGE_M) != (out_reg & BYPASS_PAGE_M)) in ixgbe_bypass_valid_rd_generic()
5072 if ((out_reg & mask) != (in_reg & mask)) in ixgbe_bypass_valid_rd_generic()
5076 if (!(out_reg & BYPASS_STATUS_OFF_M)) in ixgbe_bypass_valid_rd_generic()
5085 if ((out_reg & mask) != (in_reg & mask)) in ixgbe_bypass_valid_rd_generic()
H A Dixgbe_type.h4107 bool (*bypass_valid_rd) (u32 in_reg, u32 out_reg);
/netbsd-src/external/gpl3/gcc/dist/gcc/config/visium/
H A Dvisium.cc1037 unsigned int out_reg, in_reg; in gr5_hazard_bypass_p() local
1056 out_reg = REGNO (dest); in gr5_hazard_bypass_p()
1074 if (in_reg == out_reg) in gr5_hazard_bypass_p()
1085 if (in_reg == out_reg) in gr5_hazard_bypass_p()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/visium/
H A Dvisium.c1035 unsigned int out_reg, in_reg; in gr5_hazard_bypass_p() local
1054 out_reg = REGNO (dest); in gr5_hazard_bypass_p()
1072 if (in_reg == out_reg) in gr5_hazard_bypass_p()
1083 if (in_reg == out_reg) in gr5_hazard_bypass_p()