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/netbsd-src/external/gpl3/gcc/dist/gcc/config/nds32/
H A Dnds32-md-auxiliary.cc130 bool long_jump_p, rtx *operands) in output_cond_branch() argument
137 if (r5_p && REGNO (operands[2]) == 5 && TARGET_16_BIT) in output_cond_branch()
205 output_asm_insn (pattern, operands); in output_cond_branch()
210 bool long_jump_p, rtx *operands, in output_cond_branch_compare_zero() argument
264 output_asm_insn (pattern, operands); in output_cond_branch_compare_zero()
384 nds32_expand_cbranch (rtx *operands) in nds32_expand_cbranch() argument
389 code = GET_CODE (operands[0]); in nds32_expand_cbranch()
394 if (GET_CODE (operands[2]) == CONST_INT) in nds32_expand_cbranch()
395 if (INTVAL (operands[2]) == 0) in nds32_expand_cbranch()
409 if (GET_CODE (operands[2]) == CONST_INT) in nds32_expand_cbranch()
[all …]
H A Dnds32-doubleword.md33 if (MEM_P (operands[0]) && !REG_P (operands[1]))
34 operands[1] = force_reg (DImode, operands[1]);
43 if (MEM_P (operands[0]) && !REG_P (operands[1]))
44 operands[1] = force_reg (DFmode, operands[1]);
51 "register_operand(operands[0], <MODE>mode)
52 || register_operand(operands[1], <MODE>mode)"
64 return nds32_output_double (operands, true);
72 return nds32_output_double (operands, false);
78 return nds32_output_float_load (operands);
80 return nds32_output_float_store (operands);
[all …]
H A Dnds32-peephole2.md35 && REGNO (operands[0]) == REGNO (operands[2])
36 && REGNO (operands[0]) != REGNO (operands[1])
37 && TEST_HARD_REG_BIT (reg_class_contents[MIDDLE_REGS], REGNO (operands[0]))"
48 && REGNO (operands[0]) == REGNO (operands[3])
49 && REGNO (operands[0]) != REGNO (operands[2])
50 && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[0]))
51 && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[2]))"
61 && NDS32_IS_GPR_REGNUM (REGNO (operands[0]))
62 && NDS32_IS_GPR_REGNUM (REGNO (operands[1]))
63 && ((REGNO (operands[0]) & 0x1) == 0)
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/nds32/
H A Dnds32-md-auxiliary.c130 bool long_jump_p, rtx *operands) in output_cond_branch() argument
137 if (r5_p && REGNO (operands[2]) == 5 && TARGET_16_BIT) in output_cond_branch()
205 output_asm_insn (pattern, operands); in output_cond_branch()
210 bool long_jump_p, rtx *operands, in output_cond_branch_compare_zero() argument
264 output_asm_insn (pattern, operands); in output_cond_branch_compare_zero()
384 nds32_expand_cbranch (rtx *operands) in nds32_expand_cbranch() argument
389 code = GET_CODE (operands[0]); in nds32_expand_cbranch()
394 if (GET_CODE (operands[2]) == CONST_INT) in nds32_expand_cbranch()
395 if (INTVAL (operands[2]) == 0) in nds32_expand_cbranch()
409 if (GET_CODE (operands[2]) == CONST_INT) in nds32_expand_cbranch()
[all …]
H A Dnds32-doubleword.md33 if (MEM_P (operands[0]) && !REG_P (operands[1]))
34 operands[1] = force_reg (DImode, operands[1]);
43 if (MEM_P (operands[0]) && !REG_P (operands[1]))
44 operands[1] = force_reg (DFmode, operands[1]);
51 "register_operand(operands[0], <MODE>mode)
52 || register_operand(operands[1], <MODE>mode)"
64 return nds32_output_double (operands, true);
72 return nds32_output_double (operands, false);
78 return nds32_output_float_load (operands);
80 return nds32_output_float_store (operands);
[all …]
H A Dnds32-peephole2.md35 && REGNO (operands[0]) == REGNO (operands[2])
36 && REGNO (operands[0]) != REGNO (operands[1])
37 && TEST_HARD_REG_BIT (reg_class_contents[MIDDLE_REGS], REGNO (operands[0]))"
48 && REGNO (operands[0]) == REGNO (operands[3])
49 && REGNO (operands[0]) != REGNO (operands[2])
50 && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[0]))
51 && TEST_HARD_REG_BIT (reg_class_contents[LOW_REGS], REGNO (operands[2]))"
61 && NDS32_IS_GPR_REGNUM (REGNO (operands[0]))
62 && NDS32_IS_GPR_REGNUM (REGNO (operands[1]))
63 && ((REGNO (operands[0]) & 0x1) == 0)
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/vax/
H A Dvax.c304 split_quadword_operands (rtx insn, enum rtx_code code, rtx * operands, in split_quadword_operands() argument
314 if (MEM_P (operands[i]) in split_quadword_operands()
315 && (GET_CODE (XEXP (operands[i], 0)) == PRE_DEC in split_quadword_operands()
316 || GET_CODE (XEXP (operands[i], 0)) == POST_INC)) in split_quadword_operands()
318 rtx addr = XEXP (operands[i], 0); in split_quadword_operands()
319 operands[i] = low[i] = gen_rtx_MEM (SImode, addr); in split_quadword_operands()
321 else if (optimize_size && MEM_P (operands[i]) in split_quadword_operands()
322 && REG_P (XEXP (operands[i], 0)) in split_quadword_operands()
323 && (code != MINUS || operands[1] != const0_rtx) in split_quadword_operands()
325 REGNO (XEXP (operands[i], 0)))) in split_quadword_operands()
[all …]
H A Dvax.md120 "* return vax_output_int_move (insn, operands, DImode);")
147 && GET_CODE (operands[1]) == CONST
148 && GET_CODE (XEXP (XEXP (operands[1], 0), 0)) == SYMBOL_REF
149 && !SYMBOL_REF_LOCAL_P (XEXP (XEXP (operands[1], 0), 0)))
151 rtx symbol_ref = XEXP (XEXP (operands[1], 0), 0);
152 rtx const_int = XEXP (XEXP (operands[1], 0), 1);
153 rtx temp = reload_in_progress ? operands[0] : gen_reg_rtx (Pmode);
155 emit_move_insn (operands[0], gen_rtx_PLUS (SImode, temp, const_int));
165 "* return vax_output_int_move (insn, operands, SImode);")
171 "* return vax_output_int_move (insn, operands, <MODE>mode);")
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/m68k/
H A Dm68k.md24 ;;- operands and the removal of BCD, bitfield, rotate, and integer
160 ;; _l and _w suffixes indicate size of the operands of instruction.
258 ;; flags (but we should still verify none of the remembered operands are
301 m68k_emit_move_double (operands);
314 m68k_emit_move_double (operands);
329 rtx_code code = m68k_find_flags_value (operands[0], const0_rtx, EQ);
334 if (GET_CODE (operands[0]) == REG)
335 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
337 operands[3] = adjust_address (operands[0], SImode, 4);
338 if (! ADDRESS_REG_P (operands[0]))
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/m68k/
H A Dm68k.md24 ;;- operands and the removal of BCD, bitfield, rotate, and integer
160 ;; _l and _w suffixes indicate size of the operands of instruction.
258 ;; flags (but we should still verify none of the remembered operands are
301 m68k_emit_move_double (operands);
314 m68k_emit_move_double (operands);
329 rtx_code code = m68k_find_flags_value (operands[0], const0_rtx, EQ);
334 if (GET_CODE (operands[0]) == REG)
335 operands[3] = gen_rtx_REG (SImode, REGNO (operands[0]) + 1);
337 operands[3] = adjust_address (operands[0], SImode, 4);
338 if (! ADDRESS_REG_P (operands[0]))
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Dvec-common.md31 gcc_checking_assert (aligned_operand (operands[0], <MODE>mode));
32 gcc_checking_assert (aligned_operand (operands[1], <MODE>mode));
35 if (!REG_P (operands[0]))
36 operands[1] = force_reg (<MODE>mode, operands[1]);
38 && (CONSTANT_P (operands[1])))
40 operands[1] = neon_make_constant (operands[1]);
41 gcc_assert (operands[1] != NULL_RTX);
52 gcc_checking_assert (aligned_operand (operands[0], <MODE>mode));
53 gcc_checking_assert (aligned_operand (operands[1], <MODE>mode));
56 if (!REG_P (operands[0]))
[all …]
H A Darm.md107 ;; given instruction does not shift one of its input operands.
224 (match_test "CONSTANT_P (operands[1])"))
472 ;; Note: For DImode insns, there is normally no reason why operands should
486 if (!REG_P (operands[2]))
487 operands[2] = force_reg (DImode, operands[2]);
493 arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
495 lo_result = lo_dest = gen_lowpart (SImode, operands[0]);
496 hi_result = hi_dest = gen_highpart (SImode, operands[0]);
525 emit_move_insn (gen_highpart (SImode, operands[0]), hi_dest);
538 if (CONST_INT_P (operands[2]))
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/epiphany/
H A Depiphany.md119 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
120 operands[1] = simplify_gen_subreg (SImode, operands[1], <MODE>mode, 0);
121 emit_insn (gen_movsi (operands[0], operands[1]));
124 if (GET_CODE (operands[0]) == MEM)
125 operands[1] = force_reg (<MODE>mode, operands[1]);
127 && (operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx))
129 rtx reg = operands[0];
133 emit_insn (gen_move_frame (reg, operands[1]));
134 operands[1] = reg;
135 if (operands[0] == reg)
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/epiphany/
H A Depiphany.md119 operands[0] = simplify_gen_subreg (SImode, operands[0], <MODE>mode, 0);
120 operands[1] = simplify_gen_subreg (SImode, operands[1], <MODE>mode, 0);
121 emit_insn (gen_movsi (operands[0], operands[1]));
124 if (GET_CODE (operands[0]) == MEM)
125 operands[1] = force_reg (<MODE>mode, operands[1]);
127 && (operands[1] == frame_pointer_rtx || operands[1] == arg_pointer_rtx))
129 rtx reg = operands[0];
133 emit_insn (gen_move_frame (reg, operands[1]));
134 operands[1] = reg;
135 if (operands[0] == reg)
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/
H A Dvector.md126 if (CONSTANT_P (operands[1]))
130 if (!easy_fp_constant (operands[1], <MODE>mode))
131 operands[1] = force_const_mem (<MODE>mode, operands[1]);
133 else if (!easy_vector_constant (operands[1], <MODE>mode))
134 operands[1] = force_const_mem (<MODE>mode, operands[1]);
137 if (!vlogical_operand (operands[0], <MODE>mode)
138 && !vlogical_operand (operands[1], <MODE>mode))
139 operands[1] = force_reg (<MODE>mode, operands[1]);
149 && !gpr_or_gpr_p (operands[0], operands[1])
150 && ((memory_operand (operands[0], <MODE>mode)
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/gcn/
H A Dgcn-valu.md181 if (MEM_P (operands[0]) && !lra_in_progress && !reload_completed)
183 operands[1] = force_reg (<MODE>mode, operands[1]);
185 rtx a = gen_rtx_CONST_INT (VOIDmode, MEM_ADDR_SPACE (operands[0]));
186 rtx v = gen_rtx_CONST_INT (VOIDmode, MEM_VOLATILE_P (operands[0]));
188 operands[0],
190 emit_insn (gen_scatter<mode>_expr (expr, operands[1], a, v));
193 else if (MEM_P (operands[1]) && !lra_in_progress && !reload_completed)
196 rtx a = gen_rtx_CONST_INT (VOIDmode, MEM_ADDR_SPACE (operands[1]));
197 rtx v = gen_rtx_CONST_INT (VOIDmode, MEM_VOLATILE_P (operands[1]));
199 operands[1],
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/gcn/
H A Dgcn-valu.md181 if (MEM_P (operands[0]) && !lra_in_progress && !reload_completed)
183 operands[1] = force_reg (<MODE>mode, operands[1]);
185 rtx a = gen_rtx_CONST_INT (VOIDmode, MEM_ADDR_SPACE (operands[0]));
186 rtx v = gen_rtx_CONST_INT (VOIDmode, MEM_VOLATILE_P (operands[0]));
188 operands[0],
190 emit_insn (gen_scatter<mode>_expr (expr, operands[1], a, v));
193 else if (MEM_P (operands[1]) && !lra_in_progress && !reload_completed)
196 rtx a = gen_rtx_CONST_INT (VOIDmode, MEM_ADDR_SPACE (operands[1]));
197 rtx v = gen_rtx_CONST_INT (VOIDmode, MEM_VOLATILE_P (operands[1]));
199 operands[1],
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/h8300/
H A Dpeepholes.md15 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
34 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
53 "INTVAL (operands[3]) == (255 >> INTVAL (operands[1]))"
72 "INTVAL (operands[3]) == (255 << INTVAL (operands[1]))"
91 "INTVAL (operands[3]) == (65535 >> INTVAL (operands[1]))"
110 "INTVAL (operands[3]) == (65535 << INTVAL (operands[1]))"
131 && (REGNO_REG_CLASS (REGNO (operands[3])) == GENERAL_REGS
132 && REGNO (operands[1]) == REGNO (operands[0]) + 1
133 && REGNO (operands[2]) == REGNO (operands[0]) + 2
134 && REGNO (operands[3]) == REGNO (operands[0]) + 3
[all …]
H A Dbitfield.md25 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
42 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
55 "INTVAL (operands[2]) < 16"
68 "INTVAL (operands[2]) < 16"
70 return output_simode_bld (0, operands);
84 "INTVAL (operands[2]) < 16
85 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
101 "INTVAL (operands[2]) < 16
102 && (1 << INTVAL (operands[2])) == INTVAL (operands[3])"
104 return output_simode_bld (1, operands);
[all …]
H A Dlogical.md9 enum machine_mode mode = GET_MODE (operands[0]);
19 if ((<CODE> == AND && operands[2] == CONSTM1_RTX (mode))
20 || (<CODE> == IOR && operands[2] == CONST0_RTX (mode))
21 || (<CODE> == XOR && operands[2] == CONST0_RTX (mode))
22 || ((<CODE> == AND || <CODE> == IOR) && operands[1] == operands[2]))
24 emit_move_insn (operands[0], operands[1]);
38 "TARGET_H8300SX && rtx_equal_p (operands[0], operands[1])"
46 "TARGET_H8300SX && abs (INTVAL (operands[2])) > 0xff"
51 operands[0] = adjust_address (operands[0], QImode, 0);
52 operands[1] = adjust_address (operands[1], QImode, 0);
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Darm.md107 ;; given instruction does not shift one of its input operands.
224 (match_test "CONSTANT_P (operands[1])"))
471 ;; Note: For DImode insns, there is normally no reason why operands should
485 if (!REG_P (operands[2]))
486 operands[2] = force_reg (DImode, operands[2]);
492 arm_decompose_di_binop (operands[1], operands[2], &lo_op1, &hi_op1,
494 lo_result = lo_dest = gen_lowpart (SImode, operands[0]);
495 hi_result = hi_dest = gen_highpart (SImode, operands[0]);
524 emit_move_insn (gen_highpart (SImode, operands[0]), hi_dest);
537 if (CONST_INT_P (operands[2]))
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/
H A Dvector.md129 if (CONSTANT_P (operands[1]))
133 if (!easy_fp_constant (operands[1], <MODE>mode))
134 operands[1] = force_const_mem (<MODE>mode, operands[1]);
136 else if (!easy_vector_constant (operands[1], <MODE>mode))
137 operands[1] = force_const_mem (<MODE>mode, operands[1]);
140 if (!vlogical_operand (operands[0], <MODE>mode)
141 && !vlogical_operand (operands[1], <MODE>mode))
142 operands[1] = force_reg (<MODE>mode, operands[1]);
152 && !gpr_or_gpr_p (operands[0], operands[1])
153 && ((memory_operand (operands[0], <MODE>mode)
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/brig/brigfrontend/
H A Dbrig-cmp-inst-handler.cc58 std::vector<tree> operands = build_operands (*inst_base); in operator ()() local
64 expr = build2 (EQ_EXPR, result_type, operands[1], operands[2]); in operator ()()
68 expr = build2 (NE_EXPR, result_type, operands[1], operands[2]); in operator ()()
73 build2 (ORDERED_EXPR, result_type, operands[1], in operator ()()
74 operands[2])); in operator ()()
78 expr = build2 (LT_EXPR, result_type, operands[1], operands[2]); in operator ()()
82 expr = build2 (LE_EXPR, result_type, operands[1], operands[2]); in operator ()()
86 expr = build2 (GT_EXPR, result_type, operands[1], operands[2]); in operator ()()
90 expr = build2 (GE_EXPR, result_type, operands[1], operands[2]); in operator ()()
94 expr = build2 (UNEQ_EXPR, result_type, operands[1], operands[2]); in operator ()()
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Dsync.md47 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
48 MEM_VOLATILE_P (operands[0]) = 1;
66 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
67 MEM_VOLATILE_P (operands[0]) = 1;
85 operands[0] = gen_rtx_MEM (BLKmode, gen_rtx_SCRATCH (Pmode));
86 MEM_VOLATILE_P (operands[0]) = 1;
116 enum memmodel model = memmodel_from_int (INTVAL (operands[0]));
166 (operands[0], operands[1],
170 rtx dst = operands[0];
175 emit_move_insn (dst, operands[1]);
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/aarch64/
H A Datomics.md34 aarch64_expand_compare_and_swap (operands);
65 aarch64_split_compare_and_swap (operands);
89 aarch64_split_compare_and_swap (operands);
113 aarch64_split_compare_and_swap (operands);
130 enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
152 enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
174 enum memmodel model = memmodel_from_int (INTVAL (operands[3]));
196 (operands[0], operands[1], operands[2], operands[3]));
201 rtx func = aarch64_atomic_ool_func (mode, operands[3],
203 rtx rval = emit_library_call_value (func, operands[0], LCT_NORMAL,
[all …]

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