Home
last modified time | relevance | path

Searched refs:op5 (Results 1 – 25 of 33) sorted by relevance

12

/netbsd-src/external/gpl3/binutils.old/dist/include/opcode/
H A Dnds32.h97 #define N16_TYPE55(op5, rt5, ra5) \ argument
98 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
121 #define N16_TYPE10(op5, imm10) \ argument
122 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
/netbsd-src/external/gpl3/binutils/dist/include/opcode/
H A Dnds32.h97 #define N16_TYPE55(op5, rt5, ra5) \ argument
98 (0x8000 | __MF (N16_T55_##op5, 10, 5) | __MF (rt5, 5, 5) \
121 #define N16_TYPE10(op5, imm10) \ argument
122 (0x8000 | __MF (N16_T10_##op5, 10, 5) | __MF (imm10, 0, 10))
/netbsd-src/external/gpl3/gcc/dist/gcc/config/visium/
H A Dvisium.cc2160 rtx op5; in visium_split_double_add() local
2177 op5 = gen_int_mode (val, SImode); in visium_split_double_add()
2182 op5 = gen_lowpart (SImode, op2); in visium_split_double_add()
2187 pat = gen_negsi2_insn_set_carry (op3, op5); in visium_split_double_add()
2189 pat = gen_subsi3_insn_set_carry (op3, op4, op5); in visium_split_double_add()
2191 pat = gen_addsi3_insn_set_carry (op3, op4, op5); in visium_split_double_add()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/visium/
H A Dvisium.c2158 rtx op5; in visium_split_double_add() local
2175 op5 = gen_int_mode (val, SImode); in visium_split_double_add()
2180 op5 = gen_lowpart (SImode, op2); in visium_split_double_add()
2185 pat = gen_negsi2_insn_set_carry (op3, op5); in visium_split_double_add()
2187 pat = gen_subsi3_insn_set_carry (op3, op4, op5); in visium_split_double_add()
2189 pat = gen_addsi3_insn_set_carry (op3, op4, op5); in visium_split_double_add()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/rs6000/
H A Dvsx.md1587 rtx op5 = gen_reg_rtx (DImode);
1591 emit_insn (gen_muldi3 (op5, op3, op4));
1595 emit_move_insn (op5, ret);
1606 emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
1635 rtx op5 = gen_reg_rtx (DImode);
1639 emit_insn (gen_divdi3 (op5, op3, op4));
1644 op5, LCT_NORMAL, DImode,
1647 emit_move_insn (op5, target);
1662 emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
1682 rtx op5 = gen_reg_rtx (DImode);
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/spu/
H A Dspu.md2686 rtx op5 = operands[5];
2713 emit_insn (gen_ashrsi3 (op5, op1s, GEN_INT (31)));
2715 emit_insn (gen_spu_fsm (op3v, op5));
2720 emit_insn (gen_negsi2 (op5, op2));
2721 emit_insn (gen_rotqbybi_ti (op0, op4, op5));
2722 emit_insn (gen_rotqbi_ti (op0, op0, op5));
3312 rtx op5 = operands[5];
3316 emit_insn (gen_cgt_v4si (op5, op1, op2));
3318 emit_insn (gen_selb (op0, op5, op3, op4));
3666 rtx op5 = operands[5];
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/rs6000/
H A Dvsx.md1696 rtx op5 = gen_reg_rtx (DImode);
1700 emit_insn (gen_muldi3 (op5, op3, op4));
1704 emit_move_insn (op5, ret);
1715 emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
1745 rtx op5 = gen_reg_rtx (DImode);
1749 emit_insn (gen_divdi3 (op5, op3, op4));
1754 op5, LCT_NORMAL, DImode,
1757 emit_move_insn (op5, target);
1772 emit_insn (gen_vsx_concat_v2di (op0, op5, op3));
1797 rtx op5 = gen_reg_rtx (DImode);
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/cpu/
H A Dfr30.cpu147 (dnf f-op5 "5th bit of opcode" () 4 1)
262 ; insn-op5: bit 4 (5th bit origin 0)
264 (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5
H A Dxstormy16.cpu261 (dnf f-op5 "opcode" () 16 4)
262 (define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5
264 (dnop bcond5 "branch condition opcode" () h-branchcond f-op5)
/netbsd-src/external/gpl3/gdb.old/dist/cpu/
H A Dfr30.cpu147 (dnf f-op5 "5th bit of opcode" () 4 1)
262 ; insn-op5: bit 4 (5th bit origin 0)
264 (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5
H A Dxstormy16.cpu261 (dnf f-op5 "opcode" () 16 4)
262 (define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5
264 (dnop bcond5 "branch condition opcode" () h-branchcond f-op5)
/netbsd-src/external/gpl3/gdb/dist/cpu/
H A Dfr30.cpu147 (dnf f-op5 "5th bit of opcode" () 4 1)
262 ; insn-op5: bit 4 (5th bit origin 0)
264 (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5
H A Dxstormy16.cpu261 (dnf f-op5 "opcode" () 16 4)
262 (define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5
264 (dnop bcond5 "branch condition opcode" () h-branchcond f-op5)
/netbsd-src/external/gpl3/binutils/dist/cpu/
H A Dfr30.cpu147 (dnf f-op5 "5th bit of opcode" () 4 1)
262 ; insn-op5: bit 4 (5th bit origin 0)
264 (define-normal-insn-enum insn-op5 "insn op5 enums" () OP5_ f-op5
H A Dxstormy16.cpu261 (dnf f-op5 "opcode" () 16 4)
262 (define-normal-insn-enum insn-op5 "insn op enums" () OP5_ f-op5
264 (dnop bcond5 "branch condition opcode" () h-branchcond f-op5)
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstrFormats.td2122 class AVConv1XI<bits<5> op1, bits<2> op2, bits<4> op3, bits<4> op4, bit op5,
2128 let Inst{7} = op5; // sx
2283 bit op5, bit op4,
2293 let Inst{5} = op5;
H A DARMInstrVFP.td1761 bit op5, dag oops, dag iops, InstrItinClass itin,
1763 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
1774 bit op5, dag oops, dag iops, InstrItinClass itin,
1776 : AVConv1XI<op1, op2, op3, op4, op5, oops, iops, itin, opc, asm, pattern> {
H A DARMInstrMVE.td535 bit op5, bit op16, list<dag> pattern=[]>
545 let Inst{5} = op5;
557 class MVE_ScalarShiftDRegReg<string iname, bit op5, list<dag> pattern=[]>
560 "$RdaLo, $RdaHi, $Rm", op5, 0b0, pattern> {
565 class MVE_ScalarShiftDRegRegWithSat<string iname, bit op5, list<dag> pattern=[]>
568 "$RdaLo, $RdaHi, $sat, $Rm", op5, 0b1, pattern> {
/netbsd-src/sys/arch/aarch64/aarch64/
H A Ddisasm.c779 #define SHIFTOP8(s, op1, op2, op3, op4, op5, op6, op7, op8) \ argument
780 ((const char *[]){ op1, op2, op3, op4, op5, op6, op7, op8 })[(s) & 7]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/
H A Dsimplify-rtx.c7454 rtx op5 = make_test_reg (mode); in test_vec_merge() local
7459 rtx vm3 = gen_rtx_VEC_MERGE (mode, op4, op5, mask1); in test_vec_merge()
7493 ASSERT_RTX_EQ (gen_rtx_FMA (mode, op1, op3, op5), in test_vec_merge()
/netbsd-src/external/gpl3/gcc/dist/gcc/
H A Dsimplify-rtx.cc8205 rtx op5 = make_test_reg (mode); in test_vec_merge() local
8210 rtx vm3 = gen_rtx_VEC_MERGE (mode, op4, op5, mask1); in test_vec_merge()
8244 ASSERT_RTX_EQ (gen_rtx_FMA (mode, op1, op3, op5), in test_vec_merge()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Di386-expand.c13924 rtx ops[64], op0, op1, op2, op3, op4, op5; in ix86_expand_vector_init_general() local
14015 op5 = gen_reg_rtx (half_mode); in ix86_expand_vector_init_general()
14025 emit_insn (gen_rtx_SET (op5, gen_rtx_VEC_CONCAT (half_mode, op2, op3))); in ix86_expand_vector_init_general()
14026 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_CONCAT (mode, op4, op5))); in ix86_expand_vector_init_general()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Di386-expand.cc15715 rtx ops[64], op0, op1, op2, op3, op4, op5; in ix86_expand_vector_init_general() local
15815 op5 = gen_reg_rtx (half_mode); in ix86_expand_vector_init_general()
15825 emit_insn (gen_rtx_SET (op5, gen_rtx_VEC_CONCAT (half_mode, op2, op3))); in ix86_expand_vector_init_general()
15826 emit_insn (gen_rtx_SET (target, gen_rtx_VEC_CONCAT (mode, op4, op5))); in ix86_expand_vector_init_general()
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/s390/
H A Ds390.md8728 [; Make a backup of op5 first
8730 ; Setting op2 here might clobber op5
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Darm.md12347 rtx op5 = gen_reg_rtx (SImode);
12350 op2, op3, op4, op5));

12