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/netbsd-src/external/gpl3/autoconf/dist/tests/
H A Dautotest.at80 # Run PRE-TEST-CODE at the top level after the micro-suite is created, but
81 # before it is run, and POST-TEST-CODE after the micro-suite has been run.
85 AT_CHECK_AT_PREP([micro-suite], [$2])
87 AT_CHECK([$CONFIG_SHELL ./micro-suite $9], m4_default([$4], 0),
89 AT_CHECK([$CONFIG_SHELL ./micro-suite -v -x $9], m4_default([$4], 0),
115 AT_CHECK_AT_PREP([micro-suite], [$2], [1], [], [stderr])
154 AT_CHECK([sed 50q micro-suite | grep 'Copyright.*Free Software Foundation'],
156 AT_CHECK([sed 50q micro-suite | grep 'This is just a test notice'],
286 [AT_CHECK([[sed -n 's|.*/\([^ /]* --version\)|\1|p' micro-suite.log]], [],
297 [AT_CHECK([sed -n '/exec AS_MESSAGE_LOG_FD/q; />&AS_MESSAGE_LOG_FD/p' < micro-suite])])
[all …]
/netbsd-src/external/bsd/tre/dist/tests/agrep/
H A Dbasic.ok88 They are micro, mega, mini, mono, and multi.
98 They are micro, mega, mini, mono, and multi.
116 basic.in:They are micro, mega, mini, mono, and multi.
126 (standard input):They are micro, mega, mini, mono, and multi.
144 8:They are micro, mega, mini, mono, and multi.
154 8:They are micro, mega, mini, mono, and multi.
164 0:They are micro, mega, mini, mono, and multi.
174 0:They are micro, mega, mini, mono, and multi.
184 They are micro, mega, mini, mono, and multi.
194 They are micro, mega, mini, mono, and multi.
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/nds32/
H A Dnds32-n7.md221 ;; There are N micro-operations within an instruction that loads multiple
222 ;; words. The result produced by the M-th micro-operation is sent to
224 ;; updated, an extra micro-operation is inserted to the sequence, and the
231 ;; A double-word move instruction needs two micro-operations because the
232 ;; reigster ports is 2R1W. The first micro-operation writes an even number
233 ;; register, and the second micro-operation writes an odd number register.
234 ;; Each input operand is required at II for each micro-operation. The letter
237 ;; A MAC instruction is separated into two micro-operations. The first
238 ;; micro-operation does the multiplication, which requires operands Ra
239 ;; and Rb at II. The second micro-options does the accumulation, which
[all …]
H A Dnds32-n8.md218 ;; register port is 2R1W, two micro-operations are required in order
220 ;; micro-operation and the result is ready at EX.
222 ;; There are N micro-operations within an instruction that loads multiple
223 ;; words. The result produced by the M-th micro-operation is sent to
225 ;; updated, an extra micro-operation is inserted to the sequence, and the
235 ;; the register port is 2R1W, two micro-operations are required. The even
241 ;; remainder result to Rs. It requires two micro-operations because the
242 ;; register port is 2R1W. The first micro-operation writes to Rt, and
249 ;; The letter 'E' stands for even, which is accessed by the first micro-
252 ;; A MAC instruction is separated into two micro-operations. The first
[all …]
H A Dnds32-n9-2r1w.md267 ;; port is 2R1W, two micro-operations are required if the base register
269 ;; second micro-operation, and the updated result is ready at EX.
271 ;; There are N micro-operations within an instruction that loads multiple
272 ;; words. The result produced by the M-th micro-operation is sent to
274 ;; updated, an extra micro-operation is apppended to the end of the
287 ;; An ALU-SHIFT instruction consists of a shift micro-operation followed
288 ;; by an arithmetic micro-operation. The operand Rb is used by the first
289 ;; micro-operation, and there are some latencies if data dependency occurs.
291 ;; A double-word move instruction needs two micro-operations because the
292 ;; reigster ports is 2R1W. The first micro-operation writes an even number
[all …]
H A Dnds32-e8.md216 ;; There are N micro-operations within an instruction that loads multiple
217 ;; words. The result produced by the M-th micro-operation is sent to
227 ;; remainder result to Rs. The instruction is separated into two micro-
228 ;; operations. The first micro-operation writes to Rt, and the seconde
235 ;; N denotes the address input is required by the N-th micro-operation.
240 ;; There are N micro-operations within an instruction that stores multiple
241 ;; words. Each M-th micro-operation requires its data at EX.
/netbsd-src/external/gpl3/gcc/dist/gcc/config/nds32/
H A Dnds32-n7.md221 ;; There are N micro-operations within an instruction that loads multiple
222 ;; words. The result produced by the M-th micro-operation is sent to
224 ;; updated, an extra micro-operation is inserted to the sequence, and the
231 ;; A double-word move instruction needs two micro-operations because the
232 ;; reigster ports is 2R1W. The first micro-operation writes an even number
233 ;; register, and the second micro-operation writes an odd number register.
234 ;; Each input operand is required at II for each micro-operation. The letter
237 ;; A MAC instruction is separated into two micro-operations. The first
238 ;; micro-operation does the multiplication, which requires operands Ra
239 ;; and Rb at II. The second micro-options does the accumulation, which
[all …]
H A Dnds32-n8.md218 ;; register port is 2R1W, two micro-operations are required in order
220 ;; micro-operation and the result is ready at EX.
222 ;; There are N micro-operations within an instruction that loads multiple
223 ;; words. The result produced by the M-th micro-operation is sent to
225 ;; updated, an extra micro-operation is inserted to the sequence, and the
235 ;; the register port is 2R1W, two micro-operations are required. The even
241 ;; remainder result to Rs. It requires two micro-operations because the
242 ;; register port is 2R1W. The first micro-operation writes to Rt, and
249 ;; The letter 'E' stands for even, which is accessed by the first micro-
252 ;; A MAC instruction is separated into two micro-operations. The first
[all …]
H A Dnds32-n9-2r1w.md267 ;; port is 2R1W, two micro-operations are required if the base register
269 ;; second micro-operation, and the updated result is ready at EX.
271 ;; There are N micro-operations within an instruction that loads multiple
272 ;; words. The result produced by the M-th micro-operation is sent to
274 ;; updated, an extra micro-operation is apppended to the end of the
287 ;; An ALU-SHIFT instruction consists of a shift micro-operation followed
288 ;; by an arithmetic micro-operation. The operand Rb is used by the first
289 ;; micro-operation, and there are some latencies if data dependency occurs.
291 ;; A double-word move instruction needs two micro-operations because the
292 ;; reigster ports is 2R1W. The first micro-operation writes an even number
[all …]
H A Dnds32-e8.md216 ;; There are N micro-operations within an instruction that loads multiple
217 ;; words. The result produced by the M-th micro-operation is sent to
227 ;; remainder result to Rs. The instruction is separated into two micro-
228 ;; operations. The first micro-operation writes to Rt, and the seconde
235 ;; N denotes the address input is required by the N-th micro-operation.
240 ;; There are N micro-operations within an instruction that stores multiple
241 ;; words. Each M-th micro-operation requires its data at EX.
H A Dnds32-n9-3r2w.md280 ;; There are N micro-operations within an instruction that loads multiple
281 ;; words. The result produced by the M-th micro-operation is sent to
294 ;; An ALU-SHIFT instruction consists of a shift micro-operation followed
295 ;; by an arithmetic micro-operation. The operand Rb is used by the first
296 ;; micro-operation, and there are some latencies if data dependency occurs.
307 ;; There are N micro-operations within an instruction that stores multiple
308 ;; words. Each M-th micro-operation requires its data at MM.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64SchedKryo.td40 def KryoUnitXA : ProcResource<1>; // Type X(A) micro-ops
41 def KryoUnitXB : ProcResource<1>; // Type X(B) micro-ops
42 def KryoUnitYA : ProcResource<1>; // Type Y(A) micro-ops
43 def KryoUnitYB : ProcResource<1>; // Type Y(B) micro-ops
44 def KryoUnitX : ProcResGroup<[KryoUnitXA, // Type X micro-ops
46 def KryoUnitY : ProcResGroup<[KryoUnitYA, // Type Y micro-ops
48 def KryoUnitXY : ProcResGroup<[KryoUnitXA, // Type XY micro-ops
52 def KryoUnitLSA : ProcResource<1>; // Type LS(A) micro-ops
53 def KryoUnitLSB : ProcResource<1>; // Type LS(B) micro-ops
54 def KryoUnitLS : ProcResGroup<[KryoUnitLSA, // Type LS micro-ops
H A DAArch64SchedA57WriteRes.td22 // 11 micro-ops to be issued down one I pipe, six S pipes and four V pipes.
27 // Define Generic 1 micro-op types
61 // Define Generic 2 micro-op types
196 // Define Generic 3 micro-op types
267 // Define Generic 4 micro-op types
334 // Define Generic 5 micro-op types
378 // Define Generic 6 micro-op types
425 // Define Generic 7 micro-op types
462 // Define Generic 8 micro-op types
488 // Define Generic 9 micro-op types
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCScheduleE5500.td177 2>, // 2 micro-ops
183 2>, // 2 micro-ops
197 2>, // 2 micro-ops
203 2>, // 2 micro-ops
223 2>, // 2 micro-ops
229 2>, // 2 micro-ops
236 2>, // 2 micro-ops
243 2>, // 2 micro-ops
253 2>, // 2 micro-ops
259 2>, // 2 micro-ops
[all …]
H A DPPCScheduleE500mc.td148 2>, // 2 micro-ops
154 2>, // 2 micro-ops
164 2>, // 2 micro-ops
170 2>, // 2 micro-ops
186 2>, // 2 micro-ops
198 2>, // 2 micro-ops
205 2>, // 2 micro-ops
326 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
H A DPPCScheduleE500.td135 2>, // 2 micro-ops
141 2>, // 2 micro-ops
151 2>, // 2 micro-ops
157 2>, // 2 micro-ops
271 let IssueWidth = 2; // 2 micro-ops are dispatched per cycle.
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Support/
H A DVersionTuple.cpp64 unsigned major = 0, minor = 0, micro = 0, build = 0; in tryParse() local
91 if (parseInt(input, micro)) in tryParse()
95 *this = VersionTuple(major, minor, micro); in tryParse()
110 *this = VersionTuple(major, minor, micro, build); in tryParse()
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Dcortex-a8.md45 ;; the case where that instruction consists of only one micro-op...
50 ;; ...and in the case of two micro-ops. Dual issue is altogether forbidden
51 ;; during the issue cycle of the first micro-op. (Instead of modelling
65 ;; two micro-ops. The two micro-ops will be issued to pipeline 0 on
67 ;; first of the micro-ops.
73 ;; decomposed into three micro-ops. Dual issue cannot occur except on
74 ;; the cycle upon which the third micro-op is issued.
215 ;; as two micro-ops).
217 ;; A load multiple of three registers is usually issued as two micro-ops.
221 ;; issued as two micro-ops.
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Dcortex-a8.md45 ;; the case where that instruction consists of only one micro-op...
50 ;; ...and in the case of two micro-ops. Dual issue is altogether forbidden
51 ;; during the issue cycle of the first micro-op. (Instead of modelling
65 ;; two micro-ops. The two micro-ops will be issued to pipeline 0 on
67 ;; first of the micro-ops.
73 ;; decomposed into three micro-ops. Dual issue cannot occur except on
74 ;; the cycle upon which the third micro-op is issued.
215 ;; as two micro-ops).
217 ;; A load multiple of three registers is usually issued as two micro-ops.
221 ;; issued as two micro-ops.
/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/nvidia/
H A Dtegra186-p3310.dtsi79 shunt-resistor-micro-ohms = <10000>;
85 shunt-resistor-micro-ohms = <10000>;
91 shunt-resistor-micro-ohms = <10000>;
104 shunt-resistor-micro-ohms = <5000>;
110 shunt-resistor-micro-ohms = <10000>;
116 shunt-resistor-micro-ohms = <10000>;
H A Dtegra186-p2771-0000.dts742 shunt-resistor-micro-ohms = <20000>;
748 shunt-resistor-micro-ohms = <5000>;
754 shunt-resistor-micro-ohms = <10000>;
767 shunt-resistor-micro-ohms = <10000>;
773 shunt-resistor-micro-ohms = <10000>;
779 shunt-resistor-micro-ohms = <10000>;
886 label = "micro-USB";
887 type = "micro";
/netbsd-src/usr.sbin/acpitools/aml/
H A Daml_common.h52 #define AML_STALL(micro) OsdSleepUsec(micro) argument
59 #define AML_STALL(micro) /* not required in userland */ argument
/netbsd-src/external/apache2/llvm/dist/llvm/utils/lit/tests/Inputs/test-data-micro/
H A Dmicro-tests.ini9 [micro-tests]
14 [micro-results]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiSchedule.td30 // Max micro-ops that can be buffered for optimized loop dispatch/execution.
38 // Max micro-ops that may be scheduled per cycle. [default = 1]
47 // Max micro-ops that can be buffered. [default = -1]
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/bios/
H A Dnouveau_nvkm_subdev_bios_base.c195 bios->version.micro = nvbios_rd08(bios, bit_i.offset + 0); in nvkm_bios_new()
202 bios->version.micro = nvbios_rd08(bios, bios->bmp_offset + 10); in nvkm_bios_new()
207 bios->version.minor, bios->version.micro, bios->version.patch); in nvkm_bios_new()

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