Searched refs:max_tile_pipes (Results 1 – 18 of 18) sorted by relevance
369 *value = rdev->config.cik.max_tile_pipes; in radeon_info_ioctl()371 *value = rdev->config.si.max_tile_pipes; in radeon_info_ioctl()373 *value = rdev->config.cayman.max_tile_pipes; in radeon_info_ioctl()375 *value = rdev->config.evergreen.max_tile_pipes; in radeon_info_ioctl()377 *value = rdev->config.rv770.max_tile_pipes; in radeon_info_ioctl()379 *value = rdev->config.r600.max_tile_pipes; in radeon_info_ioctl()
1203 rdev->config.rv770.max_tile_pipes = 8; in rv770_gpu_init()1223 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1247 rdev->config.rv770.max_tile_pipes = 2; in rv770_gpu_init()1267 rdev->config.rv770.max_tile_pipes = 4; in rv770_gpu_init()1329 switch (rdev->config.rv770.max_tile_pipes) { in rv770_gpu_init()1344 rdev->config.rv770.tiling_npipes = rdev->config.rv770.max_tile_pipes; in rv770_gpu_init()
3164 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3186 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3208 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3231 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3253 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()3275 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3303 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3325 rdev->config.evergreen.max_tile_pipes = 8; in evergreen_gpu_init()3347 rdev->config.evergreen.max_tile_pipes = 4; in evergreen_gpu_init()3369 rdev->config.evergreen.max_tile_pipes = 2; in evergreen_gpu_init()[all …]
2063 unsigned max_tile_pipes; member2085 unsigned max_tile_pipes; member2112 unsigned max_tile_pipes; member2139 unsigned max_tile_pipes; member2177 unsigned max_tile_pipes; member2208 unsigned max_tile_pipes; member
2042 rdev->config.r600.max_tile_pipes = 8; in r600_gpu_init()2058 rdev->config.r600.max_tile_pipes = 2; in r600_gpu_init()2076 rdev->config.r600.max_tile_pipes = 1; in r600_gpu_init()2091 rdev->config.r600.max_tile_pipes = 4; in r600_gpu_init()2122 switch (rdev->config.r600.max_tile_pipes) { in r600_gpu_init()2138 rdev->config.r600.tiling_npipes = rdev->config.r600.max_tile_pipes; in r600_gpu_init()
3112 rdev->config.si.max_tile_pipes = 12; in si_gpu_init()3129 rdev->config.si.max_tile_pipes = 8; in si_gpu_init()3147 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3164 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3181 rdev->config.si.max_tile_pipes = 4; in si_gpu_init()3218 rdev->config.si.num_tile_pipes = rdev->config.si.max_tile_pipes; in si_gpu_init()
915 rdev->config.cayman.max_tile_pipes = 8; in cayman_gpu_init()939 rdev->config.cayman.max_tile_pipes = 2; in cayman_gpu_init()
2372 num_pipe_configs = rdev->config.cik.max_tile_pipes; in cik_tiling_mode_table_init()3206 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3223 rdev->config.cik.max_tile_pipes = 16; in cik_gpu_init()3240 rdev->config.cik.max_tile_pipes = 4; in cik_gpu_init()3259 rdev->config.cik.max_tile_pipes = 2; in cik_gpu_init()3294 rdev->config.cik.num_tile_pipes = rdev->config.cik.max_tile_pipes; in cik_gpu_init()
135 unsigned max_tile_pipes; member
1592 adev->gfx.config.max_tile_pipes = 12; in gfx_v6_0_constants_init()1609 adev->gfx.config.max_tile_pipes = 8; in gfx_v6_0_constants_init()1626 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1643 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1660 adev->gfx.config.max_tile_pipes = 4; in gfx_v6_0_constants_init()1689 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v6_0_constants_init()
4276 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4293 adev->gfx.config.max_tile_pipes = 16; in gfx_v7_0_gpu_early_init()4310 adev->gfx.config.max_tile_pipes = 4; in gfx_v7_0_gpu_early_init()4329 adev->gfx.config.max_tile_pipes = 2; in gfx_v7_0_gpu_early_init()4349 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v7_0_gpu_early_init()
1696 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1713 adev->gfx.config.max_tile_pipes = 16; in gfx_v8_0_gpu_early_init()1760 adev->gfx.config.max_tile_pipes = 8; in gfx_v8_0_gpu_early_init()1777 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1794 adev->gfx.config.max_tile_pipes = 2; in gfx_v8_0_gpu_early_init()1811 adev->gfx.config.max_tile_pipes = 4; in gfx_v8_0_gpu_early_init()1831 adev->gfx.config.num_tile_pipes = adev->gfx.config.max_tile_pipes; in gfx_v8_0_gpu_early_init()
733 adev->gfx.config.max_tile_pipes = gfx_info->info.max_tile_pipes; in amdgpu_atombios_get_gfx_info()
563 config[no_regs++] = adev->gfx.config.max_tile_pipes; in amdgpu_debugfs_gca_config_read()
1222 adev->gfx.config.max_tile_pipes = in gfx_v10_0_gpu_early_init()
2100 adev->gfx.config.max_tile_pipes = in gfx_v9_0_gpu_early_init()
1227 uint8_t max_tile_pipes; member1247 uint8_t max_tile_pipes; member
5653 UCHAR max_tile_pipes; member