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Searched refs:lower_32_bits (Results 1 – 25 of 165) sorted by relevance

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/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdkfd/
H A Dkfd_packet_manager_v9.c59 packet->sq_shader_tba_lo = lower_32_bits(qpd->tba_addr >> 8); in pm_map_process_v9()
66 packet->sq_shader_tma_lo = lower_32_bits(qpd->tma_addr >> 8); in pm_map_process_v9()
70 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_v9()
74 lower_32_bits(vm_page_table_base_addr); in pm_map_process_v9()
113 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_v9()
138 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_v9()
141 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_v9()
200 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_v9()
206 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_v9()
309 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_v9()
[all …]
H A Dkfd_packet_manager_vi.c73 packet->gds_addr_lo = lower_32_bits(qpd->gds_context_area); in pm_map_process_vi()
112 packet->ordinal2 = lower_32_bits(ib); in pm_runlist_vi()
137 packet->gws_mask_lo = lower_32_bits(res->gws_mask); in pm_set_resources_vi()
140 packet->queue_mask_lo = lower_32_bits(res->queue_mask); in pm_set_resources_vi()
190 lower_32_bits(q->gart_mqd_addr); in pm_map_queues_vi()
196 lower_32_bits((uint64_t)q->properties.write_ptr); in pm_map_queues_vi()
288 packet->addr_lo = lower_32_bits((uint64_t)fence_address); in pm_query_status_vi()
290 packet->data_lo = lower_32_bits((uint64_t)fence_value); in pm_query_status_vi()
H A Dkfd_mqd_manager_vi.c120 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
134 m->compute_tba_lo = lower_32_bits(q->tba_addr >> 8); in init_mqd()
136 m->compute_tma_lo = lower_32_bits(q->tma_addr >> 8); in init_mqd()
146 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
188 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
191 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
193 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in __update_mqd()
219 lower_32_bits(q->eop_ring_buffer_address >> 8); in __update_mqd()
361 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
363 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_v10.c116 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
132 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
181 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
184 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
186 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
207 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
338 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
340 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_v9.c151 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
172 lower_32_bits(q->ctx_save_restore_area_address); in init_mqd()
218 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd()
221 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd()
223 m->cp_hqd_pq_wptr_poll_addr_lo = lower_32_bits((uint64_t)q->write_ptr); in update_mqd()
246 lower_32_bits(q->eop_ring_buffer_address >> 8); in update_mqd()
381 m->sdmax_rlcx_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
383 m->sdmax_rlcx_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
H A Dkfd_mqd_manager_cik.c120 m->cp_mqd_base_addr_lo = lower_32_bits(addr); in init_mqd()
211 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in __update_mqd()
213 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in __update_mqd()
252 m->sdma_rlc_rb_base = lower_32_bits(q->queue_address >> 8); in update_mqd_sdma()
254 m->sdma_rlc_rb_rptr_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_sdma()
334 m->cp_hqd_pq_base_lo = lower_32_bits((uint64_t)q->queue_address >> 8); in update_mqd_hiq()
336 m->cp_hqd_pq_rptr_report_addr_lo = lower_32_bits((uint64_t)q->read_ptr); in update_mqd_hiq()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/amdgpu/
H A Damdgpu_vcn_v2_0.c324 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v2_0_mc_resume()
336 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v2_0_mc_resume()
344 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_0_mc_resume()
381 lower_32_bits(adev->vcn.inst->gpu_addr), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
402 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
422 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_0_mc_resume_dpg_mode()
860 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start_dpg_mode()
871 lower_32_bits(ring->wptr)); in vcn_v2_0_start_dpg_mode()
1014 lower_32_bits(ring->gpu_addr)); in vcn_v2_0_start()
1023 lower_32_bits(ring->wptr)); in vcn_v2_0_start()
[all …]
H A Damdgpu_vcn_v2_5.c409 lower_32_bits(adev->vcn.inst[i].gpu_addr)); in vcn_v2_5_mc_resume()
420 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset)); in vcn_v2_5_mc_resume()
428 lower_32_bits(adev->vcn.inst[i].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v2_5_mc_resume()
464 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
485 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
505 lower_32_bits(adev->vcn.inst[inst_idx].gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), 0, indirect); in vcn_v2_5_mc_resume_dpg_mode()
873 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start_dpg_mode()
884 lower_32_bits(ring->wptr)); in vcn_v2_5_start_dpg_mode()
1046 lower_32_bits(ring->gpu_addr)); in vcn_v2_5_start()
1055 lower_32_bits(ring->wptr)); in vcn_v2_5_start()
[all …]
H A Damdgpu_si_dma.c65 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in si_dma_ring_set_wptr()
77 while ((lower_32_bits(ring->wptr) & 7) != 5) in si_dma_ring_emit_ib()
163 WREG32(DMA_RB_RPTR_ADDR_LO + sdma_offsets[i], lower_32_bits(rptr_addr)); in si_dma_start()
182 WREG32(DMA_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in si_dma_start()
229 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in si_dma_ring_test_ring()
280 ib.ptr[1] = lower_32_bits(gpu_addr); in si_dma_ring_test_ib()
327 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pte()
328 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pte()
351 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_write_pte()
354 ib->ptr[ib->length_dw++] = lower_32_bits(value); in si_dma_vm_write_pte()
[all …]
H A Damdgpu_sdma_v2_4.c232 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_ring_set_wptr()
264 sdma_v2_4_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v2_4_ring_emit_ib()
269 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v2_4_ring_emit_ib()
320 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
322 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v2_4_ring_emit_fence()
328 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v2_4_ring_emit_fence()
464 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v2_4_gfx_resume()
472 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in sdma_v2_4_gfx_resume()
576 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in sdma_v2_4_ring_test_ring()
629 ib.ptr[1] = lower_32_bits(gpu_addr); in sdma_v2_4_ring_test_ib()
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H A Damdgpu_sdma_v3_0.c398 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
399 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
403 WRITE_ONCE(*wb, (lower_32_bits(ring->wptr) << 2)); in sdma_v3_0_ring_set_wptr()
405 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[ring->me], lower_32_bits(ring->wptr) << 2); in sdma_v3_0_ring_set_wptr()
438 sdma_v3_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v3_0_ring_emit_ib()
443 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v3_0_ring_emit_ib()
494 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
496 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v3_0_ring_emit_fence()
502 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v3_0_ring_emit_fence()
703 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v3_0_gfx_resume()
[all …]
H A Damdgpu_sdma_v5_0.c244 amdgpu_ring_write(ring, lower_32_bits(ring->cond_exe_gpu_addr)); in sdma_v5_0_ring_init_cond_exec()
340 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
343 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr << 2); in sdma_v5_0_ring_set_wptr()
353 lower_32_bits(ring->wptr << 2), in sdma_v5_0_ring_set_wptr()
357 lower_32_bits(ring->wptr << 2)); in sdma_v5_0_ring_set_wptr()
400 sdma_v5_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v5_0_ring_emit_ib()
405 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v5_0_ring_emit_ib()
408 amdgpu_ring_write(ring, lower_32_bits(csa_mc_addr)); in sdma_v5_0_ring_emit_ib()
461 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v5_0_ring_emit_fence()
463 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v5_0_ring_emit_fence()
[all …]
H A Damdgpu_cik_sdma.c203 (lower_32_bits(ring->wptr) << 2) & 0x3fffc); in cik_sdma_ring_set_wptr()
236 cik_sdma_ring_insert_nop(ring, (4 - lower_32_bits(ring->wptr)) & 7); in cik_sdma_ring_emit_ib()
287 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
289 amdgpu_ring_write(ring, lower_32_bits(seq)); in cik_sdma_ring_emit_fence()
295 amdgpu_ring_write(ring, lower_32_bits(addr)); in cik_sdma_ring_emit_fence()
493 WREG32(mmSDMA0_GFX_RB_WPTR + sdma_offsets[i], lower_32_bits(ring->wptr) << 2); in cik_sdma_gfx_resume()
640 amdgpu_ring_write(ring, lower_32_bits(gpu_addr)); in cik_sdma_ring_test_ring()
693 ib.ptr[1] = lower_32_bits(gpu_addr); in cik_sdma_ring_test_ib()
743 ib->ptr[ib->length_dw++] = lower_32_bits(src); in cik_sdma_vm_copy_pte()
745 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in cik_sdma_vm_copy_pte()
[all …]
H A Damdgpu_vcn_v1_0.c312 lower_32_bits(adev->vcn.inst->gpu_addr)); in vcn_v1_0_mc_resume_spg_mode()
324 lower_32_bits(adev->vcn.inst->gpu_addr + offset)); in vcn_v1_0_mc_resume_spg_mode()
332 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE)); in vcn_v1_0_mc_resume_spg_mode()
382 lower_32_bits(adev->vcn.inst->gpu_addr), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
394 lower_32_bits(adev->vcn.inst->gpu_addr + offset), 0xFFFFFFFF, 0); in vcn_v1_0_mc_resume_dpg_mode()
404 lower_32_bits(adev->vcn.inst->gpu_addr + offset + AMDGPU_VCN_STACK_SIZE), in vcn_v1_0_mc_resume_dpg_mode()
924 lower_32_bits(ring->gpu_addr)); in vcn_v1_0_start_spg_mode()
935 lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
941 WREG32_SOC15(UVD, 0, mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
942 WREG32_SOC15(UVD, 0, mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in vcn_v1_0_start_spg_mode()
[all …]
H A Damdgpu_vce_v4_0.c115 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in vce_v4_0_ring_set_wptr()
116 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
122 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
125 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
128 lower_32_bits(ring->wptr)); in vce_v4_0_ring_set_wptr()
170 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO), lower_32_bits(addr)); in vce_v4_0_mmsch_start()
241 lower_32_bits(ring->gpu_addr)); in vce_v4_0_sriov_start()
349 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
350 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_WPTR), lower_32_bits(ring->wptr)); in vce_v4_0_start()
357 WREG32(SOC15_REG_OFFSET(VCE, 0, mmVCE_RB_RPTR2), lower_32_bits(ring->wptr)); in vce_v4_0_start()
[all …]
H A Damdgpu_jpeg_v1_0.c65 val = lower_32_bits(ring->gpu_addr); in jpeg_v1_0_decode_ring_set_patch_ring()
171 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v1_0_decode_ring_set_wptr()
237 amdgpu_ring_write(ring, lower_32_bits(addr)); in jpeg_v1_0_decode_ring_emit_fence()
261 amdgpu_ring_write(ring, lower_32_bits(addr)); in jpeg_v1_0_decode_ring_emit_fence()
310 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in jpeg_v1_0_decode_ring_emit_ib()
322 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v1_0_decode_ring_emit_ib()
385 data1 = lower_32_bits(pd_addr); in jpeg_v1_0_decode_ring_emit_vm_flush()
527 WREG32_SOC15(JPEG, 0, mmUVD_LMI_JRBC_RB_64BIT_BAR_LOW, lower_32_bits(ring->gpu_addr)); in jpeg_v1_0_start()
H A Damdgpu_uvd_v7_0.c147 WREG32_SOC15(UVD, ring->me, mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v7_0_ring_set_wptr()
163 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in uvd_v7_0_enc_ring_set_wptr()
164 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
170 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
173 lower_32_bits(ring->wptr)); in uvd_v7_0_enc_ring_set_wptr()
679 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_mc_resume()
690 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset)); in uvd_v7_0_mc_resume()
697 lower_32_bits(adev->uvd.inst[i].gpu_addr + offset + AMDGPU_UVD_HEAP_SIZE)); in uvd_v7_0_mc_resume()
727 WREG32_SOC15(VCE, 0, mmVCE_MMSCH_VF_CTX_ADDR_LO, lower_32_bits(addr)); in uvd_v7_0_mmsch_start()
821 lower_32_bits(adev->uvd.inst[i].gpu_addr)); in uvd_v7_0_sriov_start()
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H A Damdgpu_vce_v3_0.c158 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
160 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
162 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_ring_set_wptr()
286 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
287 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v3_0_start()
293 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
294 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v3_0_start()
300 WREG32(mmVCE_RB_RPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start()
301 WREG32(mmVCE_RB_WPTR3, lower_32_bits(ring->wptr)); in vce_v3_0_start()
848 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in vce_v3_0_ring_emit_ib()
[all …]
H A Damdgpu_jpeg_v2_0.c366 lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_start()
451 adev->wb.wb[ring->wptr_offs] = lower_32_bits(ring->wptr); in jpeg_v2_0_dec_ring_set_wptr()
452 WDOORBELL32(ring->doorbell_index, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
454 WREG32_SOC15(JPEG, 0, mmUVD_JRBC_RB_WPTR, lower_32_bits(ring->wptr)); in jpeg_v2_0_dec_ring_set_wptr()
517 amdgpu_ring_write(ring, lower_32_bits(addr)); in jpeg_v2_0_dec_ring_emit_fence()
568 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
580 amdgpu_ring_write(ring, lower_32_bits(ring->gpu_addr)); in jpeg_v2_0_dec_ring_emit_ib()
639 data1 = lower_32_bits(pd_addr); in jpeg_v2_0_dec_ring_emit_vm_flush()
H A Damdgpu_sdma_v4_0.c706 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr()
718 lower_32_bits(ring->wptr << 2), in sdma_v4_0_ring_set_wptr()
722 lower_32_bits(ring->wptr << 2)); in sdma_v4_0_ring_set_wptr()
773 lower_32_bits(wptr)); in sdma_v4_0_page_ring_set_wptr()
808 sdma_v4_0_ring_insert_nop(ring, (2 - lower_32_bits(ring->wptr)) & 7); in sdma_v4_0_ring_emit_ib()
813 amdgpu_ring_write(ring, lower_32_bits(ib->gpu_addr) & 0xffffffe0); in sdma_v4_0_ring_emit_ib()
885 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_0_ring_emit_fence()
887 amdgpu_ring_write(ring, lower_32_bits(seq)); in sdma_v4_0_ring_emit_fence()
895 amdgpu_ring_write(ring, lower_32_bits(addr)); in sdma_v4_0_ring_emit_fence()
1115 lower_32_bits(adev->wb.gpu_addr + wb_offset) & 0xFFFFFFFC); in sdma_v4_0_gfx_resume()
[all …]
H A Damdgpu_vce_v2_0.c99 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
101 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_ring_set_wptr()
249 WREG32(mmVCE_RB_RPTR, lower_32_bits(ring->wptr)); in vce_v2_0_start()
250 WREG32(mmVCE_RB_WPTR, lower_32_bits(ring->wptr)); in vce_v2_0_start()
256 WREG32(mmVCE_RB_RPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_start()
257 WREG32(mmVCE_RB_WPTR2, lower_32_bits(ring->wptr)); in vce_v2_0_start()
H A Damdgpu_uvd_v6_0.c147 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_ring_set_wptr()
163 lower_32_bits(ring->wptr)); in uvd_v6_0_enc_ring_set_wptr()
166 lower_32_bits(ring->wptr)); in uvd_v6_0_enc_ring_set_wptr()
591 lower_32_bits(adev->uvd.inst->gpu_addr)); in uvd_v6_0_mc_resume()
833 lower_32_bits(ring->gpu_addr)); in uvd_v6_0_start()
841 WREG32(mmUVD_RBC_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
847 WREG32(mmUVD_RB_RPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
848 WREG32(mmUVD_RB_WPTR, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
854 WREG32(mmUVD_RB_RPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
855 WREG32(mmUVD_RB_WPTR2, lower_32_bits(ring->wptr)); in uvd_v6_0_start()
[all …]
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/subdev/pmu/
H A Dnouveau_nvkm_subdev_pmu_gm20b.c88 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
91 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_pmu_acr_bld_patch()
94 hdr.overlay_dma_base = lower_32_bits((addr + adjust) << 8); in gm20b_pmu_acr_bld_patch()
110 .code_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
114 .data_dma_base = lower_32_bits(data), in gm20b_pmu_acr_bld_write()
116 .overlay_dma_base = lower_32_bits(code), in gm20b_pmu_acr_bld_write()
/netbsd-src/sys/external/bsd/drm2/dist/drm/nouveau/nvkm/engine/gr/
H A Dnouveau_nvkm_engine_gr_gm20b.c46 hdr.code_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
49 hdr.data_dma_base = lower_32_bits((addr + adjust) >> 8); in gm20b_gr_acr_bld_patch()
65 .code_dma_base = lower_32_bits(code), in gm20b_gr_acr_bld_write()
69 .data_dma_base = lower_32_bits(data), in gm20b_gr_acr_bld_write()
/netbsd-src/sys/external/bsd/drm2/dist/drm/radeon/
H A Dradeon_si_dma.c86 ib->ptr[ib->length_dw++] = lower_32_bits(pe); in si_dma_vm_copy_pages()
87 ib->ptr[ib->length_dw++] = lower_32_bits(src); in si_dma_vm_copy_pages()
269 radeon_ring_write(ring, lower_32_bits(dst_offset)); in si_copy_dma()
270 radeon_ring_write(ring, lower_32_bits(src_offset)); in si_copy_dma()

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