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/netbsd-src/external/bsd/elftosb/dist/bdfiles/
H A Dbasic_test_cmd.e44 # load dcd
45 load dcd {{ 00 11 22 33 }} > 0;
47 # same load without dcd
48 load {{ 00 11 22 33 }} > 0;
56 # load a simple IVT to an absolute address
58 load ivt (entry=hello:_start) > 0x1000;
60 # load simple IVT. the IVT self address is set explicitly in the IVT declaration,
61 # giving the IVT a natural address so you don't have to tell where to load it.
62 load ivt (entry=hello:_start, self=0x1000);
64 load ivt (entry=hello:_start, self=0x1000, csf=0x2000, dcd=0);
[all …]
H A Dtest_cmd.e64 # load 0.w > ocram_start..ocram_end; # word fill all ocram with 0
66 # load hostlink; # load all of hostlink source
68 # load 0x1000ffff.w > 0x1000; # load a word to address 0x1000
69 # load 0x55aa.h > 0x2000; # load a half-word to address 0x2000
70 # load redboot; # load all sections of redboot source
73 # load $.*.text; # load some sections to their natural location
79 # load $* > .; # load all sections of hostlink to their natural location
81 # load $.text > 0x1000; # load .text section to address 0x1000
83 # load 0x55.b > 0x0..0x4000; # fill 0 through 0x4000 with byte pattern 0x55
86 # load $*.text from hostlink > .; # load sections match "*.text" from hostlink to default places
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H A Dcomplex.bd81 load dcd {{ 00 11 22 33 }} > 0;
82 load srecfile;
107 load 0x1234.h > 0..10K;
113 load halfword > 0..1K;
120 load 0xff.b > 32K..32K + sizeof(elffile:printMessage);
123 load {{ 00 01 02 03 04 }} > 1K;
125 // load all sections except .mytext
126 load ~$.mytext;
132 load "hi from section 1" > :szMsg;
139 load 0.w > (elffile:endOfLine)..(elffile:endOfLine + sizeof(elffile:endOfLine));
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/netbsd-src/tests/lib/libc/stdlib/
H A Dt_getopt.sh31 load: $1
57 load="c:d"
59 h_getopt "${load}" "foo -c 1 -d foo" "c=1,d|1"
60 h_getopt "${load}" "foo -d foo bar" "d|2"
61 h_getopt "${load}" "foo -c 2 foo bar" "c=2|2"
62 h_getopt "${load}" "foo -e 1 foo bar" "!?|3"
63 h_getopt "${load}" "foo -d -- -c 1" "d|2"
64 h_getopt "${load}" "foo -c- 1" "c=-|1"
65 h_getopt "${load}" "foo -d - 1" "d|2"
88 load="optstring: abc:
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/netbsd-src/external/gpl3/gcc/dist/gcc/config/i386/
H A Dbtver2.md65 ;; There are 2 AGU pipes one for load and one for store.
67 (define_cpu_unit "btver2-load" "btver2_agu")
80 btver2-load+btver2-store")
95 btver2-load+btver2-store")
101 "btver2-double,btver2-load")
108 (and (eq_attr "memory" "load")
110 "btver2-direct,btver2-load,btver2-alu")
119 (and (eq_attr "memory" "load")
121 "btver2-direct,btver2-load,btver2-alu")
156 (eq_attr "memory" "load,both"))))
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H A Dznver4.md62 ;; Load is 4 cycles. We do not model reservation of load unit.
63 (define_reservation "znver4-load" "znver4-agu-reserve")
107 (eq_attr "memory" "load"))))
108 "znver4-double,znver4-load,znver4-ieu")
120 (eq_attr "memory" "load")))
121 "znver4-direct,znver4-load,znver4-ieu")
134 "znver4-direct,znver4-load,znver4-store")
140 (eq_attr "memory" "load")))
141 "znver4-direct,znver4-load")
147 "znver4-direct,znver4-load,znver4-store")
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H A Dznver.md63 ;; Load is 4 cycles. We do not model reservation of load unit.
64 ;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing")
65 (define_reservation "znver1-load" "znver1-agu-reserve")
123 "znver1-direct,znver1-load,znver1-store")
128 "znver1-direct,znver1-load,znver2-store")
133 (eq_attr "memory" "load")))
134 "znver1-direct,znver1-load")
140 "znver1-direct,znver1-load,znver1-store")
145 "znver1-direct,znver1-load,znver2-store")
170 "znver1-direct,znver1-load, znver1-ieu1")
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H A Dathlon.md35 ;; The load/store queue unit is not attached to the schedulers but
45 (and (eq_attr "memory" "load,store")
64 ;; imul load/store (2x) fadd fmul fstore
118 (define_reservation "athlon-load" "athlon-agu,
135 (define_reservation "athlon-fpload" "(athlon-fpsched + athlon-load)")
137 (define_reservation "athlon-fploadk8" "(athlon-fpsched + athlon-load)")
175 "athlon-vector,athlon-load,athlon-ieu")
179 "athlon-double,(athlon-ieu+athlon-load)")
183 "athlon-direct,(athlon-ieu+athlon-load)")
187 "athlon-vector,(athlon-ieu+athlon-load)")
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H A Dbdver3.md27 ;; The load/store queue unit is not attached to the schedulers but
64 (define_reservation "bdver3-load" "bdver3-agu,
83 (define_reservation "bdver3-fpload" "(bdver3-fpsched + bdver3-load)")
144 (eq_attr "memory" "load,both"))))
145 "bdver3-direct,bdver3-load,bdver3-ieu1")
149 (eq_attr "memory" "load,both")))
150 "bdver3-direct,bdver3-load,bdver3-ieu1")
155 (eq_attr "memory" "load,both,store")))
156 "bdver3-vector,bdver3-load,bdver3-ivector")
174 (eq_attr "memory" "load")))
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H A Dbdver1.md32 ;; The load/store queue unit is not attached to the schedulers but
84 (define_reservation "bdver1-load" "bdver1-agu,
108 (define_reservation "bdver1-fpload" "(bdver1-fpsched + bdver1-load)")
170 (eq_attr "memory" "load,both"))))
171 "bdver1-direct1,bdver1-load,bdver1-ieu1")
175 (eq_attr "memory" "load,both")))
176 "bdver1-direct1,bdver1-load,bdver1-ieu1")
193 (eq_attr "memory" "load,both")))
194 "bdver1-vector,((bdver1-load,bdver1-ieu0*6)+(bdver1-fpsched,bdver1-fvector))")
202 (eq_attr "memory" "load,both,store")))
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/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/i386/
H A Dbtver2.md65 ;; There are 2 AGU pipes one for load and one for store.
67 (define_cpu_unit "btver2-load" "btver2_agu")
80 btver2-load+btver2-store")
95 btver2-load+btver2-store")
101 "btver2-double,btver2-load")
108 (and (eq_attr "memory" "load")
110 "btver2-direct,btver2-load,btver2-alu")
119 (and (eq_attr "memory" "load")
121 "btver2-direct,btver2-load,btver2-alu")
156 (eq_attr "memory" "load,both"))))
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H A Dznver1.md63 ;; Load is 4 cycles. We do not model reservation of load unit.
64 ;;(define_reservation "znver1-load" "znver1-agu-reserve, nothing, nothing, nothing")
65 (define_reservation "znver1-load" "znver1-agu-reserve")
123 "znver1-direct,znver1-load,znver1-store")
128 "znver1-direct,znver1-load,znver2-store")
133 (eq_attr "memory" "load")))
134 "znver1-direct,znver1-load")
140 "znver1-direct,znver1-load,znver1-store")
145 "znver1-direct,znver1-load,znver2-store")
170 "znver1-direct,znver1-load, znver1-ieu1")
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H A Dathlon.md35 ;; The load/store queue unit is not attached to the schedulers but
45 (and (eq_attr "memory" "load,store")
64 ;; imul load/store (2x) fadd fmul fstore
118 (define_reservation "athlon-load" "athlon-agu,
135 (define_reservation "athlon-fpload" "(athlon-fpsched + athlon-load)")
137 (define_reservation "athlon-fploadk8" "(athlon-fpsched + athlon-load)")
175 "athlon-vector,athlon-load,athlon-ieu")
179 "athlon-double,(athlon-ieu+athlon-load)")
183 "athlon-direct,(athlon-ieu+athlon-load)")
187 "athlon-vector,(athlon-ieu+athlon-load)")
[all …]
H A Dbdver3.md27 ;; The load/store queue unit is not attached to the schedulers but
64 (define_reservation "bdver3-load" "bdver3-agu,
83 (define_reservation "bdver3-fpload" "(bdver3-fpsched + bdver3-load)")
144 (eq_attr "memory" "load,both"))))
145 "bdver3-direct,bdver3-load,bdver3-ieu1")
149 (eq_attr "memory" "load,both")))
150 "bdver3-direct,bdver3-load,bdver3-ieu1")
155 (eq_attr "memory" "load,both,store")))
156 "bdver3-vector,bdver3-load,bdver3-ivector")
174 (eq_attr "memory" "load")))
[all …]
H A Dbdver1.md32 ;; The load/store queue unit is not attached to the schedulers but
84 (define_reservation "bdver1-load" "bdver1-agu,
108 (define_reservation "bdver1-fpload" "(bdver1-fpsched + bdver1-load)")
170 (eq_attr "memory" "load,both"))))
171 "bdver1-direct1,bdver1-load,bdver1-ieu1")
175 (eq_attr "memory" "load,both")))
176 "bdver1-direct1,bdver1-load,bdver1-ieu1")
193 (eq_attr "memory" "load,both")))
194 "bdver1-vector,((bdver1-load,bdver1-ieu0*6)+(bdver1-fpsched,bdver1-fvector))")
202 (eq_attr "memory" "load,both,store")))
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/netbsd-src/sys/external/gpl2/dts/dist/arch/arm64/boot/dts/qcom/
H A Dmsm8994-msft-lumia-octagon.dtsi31 * Most Lumia 950/XL users use GRUB to load their kernels,
587 regulator-allow-set-load;
588 regulator-system-load = <300000>;
594 regulator-allow-set-load;
596 regulator-system-load = <325000>;
602 regulator-allow-set-load;
603 regulator-system-load = <325000>;
624 regulator-allow-set-load;
625 regulator-system-load = <4160>;
632 regulator-allow-set-load;
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZInstrHFP.td137 def AE : BinaryRX<"ae", 0x7A, null_frag, FP32, load, 4>;
138 def AD : BinaryRX<"ad", 0x6A, null_frag, FP64, load, 8>;
147 def AU : BinaryRX<"au", 0x7E, null_frag, FP32, load, 4>;
148 def AW : BinaryRX<"aw", 0x6E, null_frag, FP64, load, 8>;
157 def SE : BinaryRX<"se", 0x7B, null_frag, FP32, load, 4>;
158 def SD : BinaryRX<"sd", 0x6B, null_frag, FP64, load, 8>;
166 def SU : BinaryRX<"su", 0x7F, null_frag, FP32, load, 4>;
167 def SW : BinaryRX<"sw", 0x6F, null_frag, FP64, load, 8>;
176 def MEE : BinaryRXE<"mee", 0xED37, null_frag, FP32, load, 4>;
177 def MD : BinaryRX <"md", 0x6C, null_frag, FP64, load, 8>;
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H A DSystemZPatterns.td42 class RMWI<SDPatternOperator load, SDPatternOperator operator,
45 : Pat<(store (operator (load mode:$addr), imm:$src), mode:$addr),
59 SDPatternOperator load, AddressingMode mode> {
61 cls:$src1, (load mode:$src2)),
64 (load mode:$src2), cls:$src1),
100 SDPatternOperator store, SDPatternOperator load,
102 def : Pat<(store (z_select_ccmask GR64:$new, (load mode:$addr),
107 def : Pat<(store (z_select_ccmask (load mode:$addr), GR64:$new,
114 // Try to use MVC instruction INSN for a load of type LOAD followed by a store
117 multiclass MVCLoadStore<SDPatternOperator load, ValueType vt, Instruction insn,
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/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Ds390-opc.txt85 58 l RX_RRRD "load" g5 esa,zarch
86 41 la RX_RRRD "load address" g5 esa,zarch
87 51 lae RX_RRRD "load address extended" g5 esa,zarch
88 9a lam RS_AARD "load access multiple" g5 esa,zarch
89 e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch
90 23 lcdr RR_FF "load complement (long)" g5 esa,zarch
91 33 lcer RR_FF "load complement (short)" g5 esa,zarch
92 13 lcr RR_RR "load complement" g5 esa,zarch
93 b7 lctl RS_CCRD "load control" g5 esa,zarch
94 68 ld RX_FRRD "load (long)" g5 esa,zarch
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/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Ds390-opc.txt85 58 l RX_RRRD "load" g5 esa,zarch
86 41 la RX_RRRD "load address" g5 esa,zarch
87 51 lae RX_RRRD "load address extended" g5 esa,zarch
88 9a lam RS_AARD "load access multiple" g5 esa,zarch
89 e500 lasp SSE_RDRD "load address space parameters" g5 esa,zarch
90 23 lcdr RR_FF "load complement (long)" g5 esa,zarch
91 33 lcer RR_FF "load complement (short)" g5 esa,zarch
92 13 lcr RR_RR "load complement" g5 esa,zarch
93 b7 lctl RS_CCRD "load control" g5 esa,zarch
94 68 ld RX_FRRD "load (long)" g5 esa,zarch
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/netbsd-src/external/lgpl3/gmp/dist/mpn/arm/neon/
H A Dhamdist.asm78 vld1.32 {d0[0]}, [ap]! C load 1 limb
79 vld1.32 {d20[0]}, [bp]! C load 1 limb
87 vld1.32 {d0}, [ap]! C load 2 limbs
88 vld1.32 {d20}, [bp]! C load 2 limbs
96 vld1.32 {q0}, [ap]! C load 4 limbs
97 vld1.32 {q10}, [bp]! C load 4 limbs
106 vld1.32 {q0,q1}, [ap]! C load 8 limbs
107 vld1.32 {q10,q11}, [bp]! C load 8 limbs
110 L(gt8): vld1.32 {q2,q3}, [ap]! C load 8 limbs
111 vld1.32 {q14,q15}, [bp]! C load 8 limbs
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/netbsd-src/external/bsd/kyua-cli/dist/engine/
H A Dkyuafile_test.cpp57 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
98 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
145 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
189 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
225 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
266 const engine::kyuafile suite = engine::kyuafile::load( in ATF_TEST_CASE_BODY()
300 engine::kyuafile::load(fs::path("config"), none)); in ATF_TEST_CASE_BODY()
309 ATF_REQUIRE_THROW(engine::load_error, engine::kyuafile::load( in ATF_TEST_CASE_BODY()
320 engine::kyuafile::load(fs::path("config"), none)); in ATF_TEST_CASE_BODY()
328 (void)engine::kyuafile::load(fs::path("config"), none); in ATF_TEST_CASE_BODY()
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/netbsd-src/crypto/external/bsd/openssl.old/lib/libcrypto/arch/arm/
H A Dchacha-armv4.S60 ldmia r12,{r4,r5,r6,r7} @ load counter and nonce
61 sub sp,sp,#4*(16) @ off-load area
64 ldmia r3,{r4,r5,r6,r7,r8,r9,r10,r11} @ load key
65 ldmia r14,{r0,r1,r2,r3} @ load sigma
68 str r10,[sp,#4*(16+10)] @ off-load "rx"
69 str r11,[sp,#4*(16+11)] @ off-load "rx"
74 ldmia sp,{r0,r1,r2,r3,r4,r5,r6,r7,r8,r9} @ load key material
80 ldr r12,[sp,#4*(12)] @ modulo-scheduled load
200 ldr r11,[sp,#4*(32+2)] @ load len
216 ldrhs r12,[sp,#4*(32+1)] @ ... load inp
[all …]
/netbsd-src/crypto/external/bsd/openssl/lib/libcrypto/arch/arm/
H A Dchacha-armv4.S67 ldmia r12,{r4,r5,r6,r7} @ load counter and nonce
68 sub sp,sp,#4*(16) @ off-load area
71 ldmia r3,{r4,r5,r6,r7,r8,r9,r10,r11} @ load key
72 ldmia r14,{r0,r1,r2,r3} @ load sigma
75 str r10,[sp,#4*(16+10)] @ off-load "rx"
76 str r11,[sp,#4*(16+11)] @ off-load "rx"
81 ldmia sp,{r0,r1,r2,r3,r4,r5,r6,r7,r8,r9} @ load key material
87 ldr r12,[sp,#4*(12)] @ modulo-scheduled load
207 ldr r11,[sp,#4*(32+2)] @ load len
223 ldrhs r12,[sp,#4*(32+1)] @ ... load inp
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/netbsd-src/crypto/external/bsd/heimdal/dist/lib/hcrypto/
H A Ddes.c328 load(const unsigned char *b, uint32_t v[2]) in load() function
387 load(*input, u); in DES_ecb_encrypt()
416 load(*iv, uiv); in DES_cbc_encrypt()
420 load(input, u); in DES_cbc_encrypt()
434 load(tmp, u); in DES_cbc_encrypt()
442 load(input, u); in DES_cbc_encrypt()
457 load(tmp, u); in DES_cbc_encrypt()
492 load(*iv, uiv); in DES_pcbc_encrypt()
497 load(input, u); in DES_pcbc_encrypt()
512 load(tmp, u); in DES_pcbc_encrypt()
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