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Searched refs:isVGPR (Results 1 – 11 of 11) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIRegisterInfo.h229 bool isVGPR(const MachineRegisterInfo &MRI, Register Reg) const;
232 return isVGPR(MRI, Reg) || isAGPR(MRI, Reg); in isVectorRegister()
H A DSIFoldOperands.cpp425 !TII->getRegisterInfo().isVGPR(MRI, OtherOp.getReg())) in tryAddToFoldList()
832 TRI->isVGPR(*MRI, UseMI->getOperand(1).getReg())) in foldOperand()
834 else if (TRI->isVGPR(*MRI, UseMI->getOperand(0).getReg()) && in foldOperand()
1516 if (!ST->hasGFX90AInsts() || !TRI->isVGPR(*MRI, Reg) || in tryFoldRegSequence()
1542 if (!TRI->isVGPR(*MRI, Reg) || !MRI->hasOneNonDBGUse(Reg)) in tryFoldRegSequence()
1616 !TRI->isVGPR(*MRI, PhiIn) || !TRI->isVGPR(*MRI, PhiOut)) in tryFoldLCSSAPhi()
1660 if (DefReg.isPhysical() || !TRI->isVGPR(*MRI, DefReg)) in tryFoldLoad()
H A DSIPreAllocateWWMRegs.cpp95 if (!TRI->isVGPR(*MRI, Reg)) in processDef()
H A DSIShrinkInstructions.cpp485 if (!TRI.isVGPR(MRI, X)) in matchSwap()
512 if (!TRI.isVGPR(MRI, Y)) in matchSwap()
H A DGCNHazardRecognizer.cpp651 if (!Use.isReg() || !TRI->isVGPR(MF.getRegInfo(), Use.getReg())) in checkDPPHazards()
1222 if (!Use.isReg() || !TRI.isVGPR(MF.getRegInfo(), Use.getReg())) in checkMAIHazards908()
1536 if (!Op.isReg() || !TRI.isVGPR(MF.getRegInfo(), Op.getReg())) in checkMAILdStHazards()
H A DSIWholeQuadMode.cpp859 if (TRI->isVGPR(*MRI, Op0.getReg())) { in lowerKillF32()
1430 if (TRI->isVGPR(*MRI, Reg)) { in lowerCopyInstrs()
H A DSIInstrInfo.h741 return MO.isReg() && RI.isVGPR(MRI, MO.getReg());}); in hasVGPRUses()
H A DSIInstrInfo.cpp2725 bool isVGPRCopy = RI.isVGPR(*MRI, DstReg); in FoldImmediate()
3511 if (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg())) in canShrink()
3521 if (!Src2->isReg() || !RI.isVGPR(MRI, Src2->getReg()) || in canShrink()
3532 if (Src1 && (!Src1->isReg() || !RI.isVGPR(MRI, Src1->getReg()) || in canShrink()
4747 if (Src0.isReg() && RI.isVGPR(MRI, Src0.getReg())) { in legalizeOperandsVOP2()
4753 if (Src1.isReg() && RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
4779 RI.isVGPR(MRI, Src1.getReg())) { in legalizeOperandsVOP2()
H A DSIRegisterInfo.cpp937 unsigned Opc = (IsStore ^ TRI->isVGPR(MRI, Reg)) ? AMDGPU::V_ACCVGPR_WRITE_B32_e64 in spillVGPRtoAGPR()
2242 bool SIRegisterInfo::isVGPR(const MachineRegisterInfo &MRI, in isVGPR() function in SIRegisterInfo
H A DSIPeepholeSDWA.cpp1168 if (!Op.isImm() && !(Op.isReg() && !TRI->isVGPR(*MRI, Op.getReg()))) in legalizeScalarOperands()
H A DSIInsertWaitcnts.cpp607 TRI->isVGPR(*MRI, DefMO.getReg())) { in updateByEvent()