Searched refs:isSubRegister (Results 1 – 15 of 15) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/MC/ |
| H A D | MCInstrDesc.cpp | 37 if (*ImpDefs == Reg || (MRI && MRI->isSubRegister(Reg, *ImpDefs))) in hasImplicitDefOfPhysReg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/AsmPrinter/ |
| H A D | DwarfExpression.h | 125 bool isSubRegister() const { return SubRegSize; } in isSubRegister() function
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| H A D | DwarfExpression.cpp | 328 assert(!Reg.isSubRegister() && "full register expected"); in addMachineRegExpression()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/ |
| H A D | HexagonMCChecker.cpp | 592 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
605 unsigned BadR = RI.isSubRegister(Hexagon::USR, R) ? UsrR : R; in checkRegisters()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | AggressiveAntiDepBreaker.cpp | 593 bool IsSub = TRI->isSubRegister(SuperReg, Reg); in FindSuitableFreeRegisters()
927 if (R == AntiDepReg || TRI->isSubRegister(AntiDepReg, R)) in BreakAntiDependencies()
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| H A D | MachineInstr.cpp | 1058 Found = TRI->isSubRegister(MOReg, Reg); in findRegisterDefOperandIdx()
1916 if (RegInfo->isSubRegister(IncomingReg, Reg)) in addRegisterKilled()
1981 if (RegInfo->isSubRegister(Reg, MOReg)) in addRegisterDead()
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| H A D | MachineCopyPropagation.cpp | 342 if (!TRI->isSubRegister(PreviousSrc, Src)) in isNopCopy()
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| H A D | LiveVariables.cpp | 217 if (TRI->isSubRegister(Reg, DefReg)) { in FindLastPartialDef()
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCRegisterInfo.h | 560 bool isSubRegister(MCRegister RegA, MCRegister RegB) const { in isSubRegister() function
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | SIRegisterInfo.cpp | 556 assert(!isSubRegister(ScratchRSrcReg, StackPtrReg)); in getReservedRegs()
562 assert(!isSubRegister(ScratchRSrcReg, FrameReg)); in getReservedRegs()
568 assert(!isSubRegister(ScratchRSrcReg, BasePtrReg)); in getReservedRegs()
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| H A D | SIInstrInfo.cpp | 3689 return TRI.isSubRegister(SuperVec.getReg(), SubReg.getReg()); in isSubRegOf()
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| H A D | SIISelLowering.cpp | 11775 assert(!TRI->isSubRegister(Info->getScratchRSrcReg(), in finalizeLowering()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsInstrInfo.cpp | 868 if (TRI->isSuperRegister(Reg, DestReg) || TRI->isSubRegister(Reg, DestReg)) in describeLoadedValue()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64LoadStoreOptimizer.cpp | 1910 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnForward()
1981 if (DestReg == BaseReg || TRI->isSubRegister(BaseReg, DestReg)) in findMatchingUpdateInsnBackward()
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| H A D | AArch64InstrInfo.cpp | 7464 TRI->isSubRegister(DestReg, DescribedReg)) { in describeORRLoadedValue()
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