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Searched refs:isSubClassOf (Results 1 – 25 of 39) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DPredicateExpander.cpp64 assert(Reg->isSubClassOf("Register") && "Expected a register Record!"); in expandCheckRegOperand()
285 if (Rec->isSubClassOf("MCOpcodeSwitchStatement")) { in expandStatement()
291 if (Rec->isSubClassOf("MCReturnStatement")) { in expandStatement()
301 if (Rec->isSubClassOf("MCTrue")) { in expandPredicate()
307 if (Rec->isSubClassOf("MCFalse")) { in expandPredicate()
313 if (Rec->isSubClassOf("CheckNot")) { in expandPredicate()
320 if (Rec->isSubClassOf("CheckIsRegOperand")) in expandPredicate()
323 if (Rec->isSubClassOf("CheckIsImmOperand")) in expandPredicate()
326 if (Rec->isSubClassOf("CheckRegOperand")) in expandPredicate()
331 if (Rec->isSubClassOf("CheckRegOperandSimple")) in expandPredicate()
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H A DCallingConvEmitter.cpp98 if (Action->isSubClassOf("CCPredicateAction")) { in EmitAction()
101 if (Action->isSubClassOf("CCIfType")) { in EmitAction()
109 } else if (Action->isSubClassOf("CCIf")) { in EmitAction()
120 if (Action->isSubClassOf("CCDelegateTo")) { in EmitAction()
125 } else if (Action->isSubClassOf("CCAssignToReg")) { in EmitAction()
145 } else if (Action->isSubClassOf("CCAssignToRegWithShadow")) { in EmitAction()
185 } else if (Action->isSubClassOf("CCAssignToStack")) { in EmitAction()
210 } else if (Action->isSubClassOf("CCAssignToStackWithShadow")) { in EmitAction()
231 } else if (Action->isSubClassOf("CCPromoteToType")) { in EmitAction()
245 } else if (Action->isSubClassOf("CCPromoteToUpperBitsInType")) { in EmitAction()
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H A DCodeGenInstruction.cpp83 if (Rec->isSubClassOf("RegisterOperand")) { in CGIOperandList()
88 } else if (Rec->isSubClassOf("Operand")) { in CGIOperandList()
108 if (Rec->isSubClassOf("PredicateOp")) in CGIOperandList()
110 else if (Rec->isSubClassOf("OptionalDefOperand")) in CGIOperandList()
117 } else if (Rec->isSubClassOf("RegisterClass")) { in CGIOperandList()
119 } else if (!Rec->isSubClassOf("PointerLikeRegClass") && in CGIOperandList()
120 !Rec->isSubClassOf("unknown_class")) in CGIOperandList()
458 assert(FirstImplicitDef->isSubClassOf("Register")); in HasOneImplicitDefWithKnownVT()
524 return Constraint->getDef()->isSubClassOf("TypedOperand") && in isOperandImpl()
557 if (InstOpRec->isSubClassOf("RegisterOperand")) in tryAliasOpMatch()
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H A DDAGISelMatcherGen.cpp234 if (LeafRec->isSubClassOf("ValueType")) { in EmitLeafMatchCode()
243 LeafRec->isSubClassOf("RegisterClass") || in EmitLeafMatchCode()
244 LeafRec->isSubClassOf("RegisterOperand") || in EmitLeafMatchCode()
245 LeafRec->isSubClassOf("PointerLikeRegClass") || in EmitLeafMatchCode()
246 LeafRec->isSubClassOf("SubRegIndex") || in EmitLeafMatchCode()
253 if (LeafRec->isSubClassOf("Register")) { in EmitLeafMatchCode()
260 if (LeafRec->isSubClassOf("CondCode")) in EmitLeafMatchCode()
263 if (LeafRec->isSubClassOf("ComplexPattern")) { in EmitLeafMatchCode()
314 if (N->getOperator()->isSubClassOf("ComplexPattern")) { in EmitOperatorMatchCode()
684 if (Def->isSubClassOf("Register")) { in EmitResultLeafAsOperand()
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H A DInfoByHwMode.cpp42 if (R->isSubClassOf("PtrValueType")) in ValueTypeByHwMode()
109 if (!Rec->isSubClassOf("ValueType")) in getValueTypeByHwMode()
112 assert(Rec->isSubClassOf("ValueType") && in getValueTypeByHwMode()
114 if (Rec->isSubClassOf("HwModeSelect")) in getValueTypeByHwMode()
130 bool RegSizeInfo::isSubClassOf(const RegSizeInfo &I) const { in isSubClassOf() function in RegSizeInfo
161 bool RegSizeInfoByHwMode::isSubClassOf(const RegSizeInfoByHwMode &I) const { in isSubClassOf() function in RegSizeInfoByHwMode
163 return get(M0).isSubClassOf(I.get(M0)); in isSubClassOf()
192 assert(P.second && P.second->isSubClassOf("InstructionEncoding") && in EncodingInfoByHwMode()
H A DCodeGenDAGPatterns.cpp1451 if (!Def->isSubClassOf("Predicate")) { in getPredicateRecords()
1499 if (R->isSubClassOf("SDTCisVT")) { in SDTypeConstraint()
1505 } else if (R->isSubClassOf("SDTCisPtrTy")) { in SDTypeConstraint()
1507 } else if (R->isSubClassOf("SDTCisInt")) { in SDTypeConstraint()
1509 } else if (R->isSubClassOf("SDTCisFP")) { in SDTypeConstraint()
1511 } else if (R->isSubClassOf("SDTCisVec")) { in SDTypeConstraint()
1513 } else if (R->isSubClassOf("SDTCisSameAs")) { in SDTypeConstraint()
1516 } else if (R->isSubClassOf("SDTCisVTSmallerThanOp")) { in SDTypeConstraint()
1520 } else if (R->isSubClassOf("SDTCisOpSmallerThanOp")) { in SDTypeConstraint()
1524 } else if (R->isSubClassOf("SDTCisEltOfVec")) { in SDTypeConstraint()
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H A DCodeGenTarget.cpp712 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
714 if (TyEl->isSubClassOf("LLVMMatchType")) in CodeGenIntrinsic()
729 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
731 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
739 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && in CodeGenIntrinsic()
740 !TyEl->isSubClassOf("LLVMTruncatedType")) || in CodeGenIntrinsic()
760 assert(TyEl->isSubClassOf("LLVMType") && "Expected a type!"); in CodeGenIntrinsic()
762 if (TyEl->isSubClassOf("LLVMMatchType")) { in CodeGenIntrinsic()
775 assert(((!TyEl->isSubClassOf("LLVMExtendedType") && in CodeGenIntrinsic()
776 !TyEl->isSubClassOf("LLVMTruncatedType")) || in CodeGenIntrinsic()
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H A DX86EVEX2VEXTablesEmitter.cpp166 return Rec->isSubClassOf("RegisterClass") || in isRegisterOperand()
167 Rec->isSubClassOf("RegisterOperand"); in isRegisterOperand()
171 return Rec->isSubClassOf("Operand") && in isMemoryOperand()
176 return Rec->isSubClassOf("Operand") && in isImmediateOperand()
181 if (RegRec->isSubClassOf("RegisterClass")) in getRegOperandSize()
183 if (RegRec->isSubClassOf("RegisterOperand")) in getRegOperandSize()
210 if (!Inst->TheDef->isSubClassOf("X86Inst")) in run()
H A DIntrinsicEmitter.cpp297 if (R->isSubClassOf("LLVMMatchType")) { in EncodeFixedType()
300 if (R->isSubClassOf("LLVMExtendedType")) in EncodeFixedType()
302 else if (R->isSubClassOf("LLVMTruncatedType")) in EncodeFixedType()
304 else if (R->isSubClassOf("LLVMHalfElementsVectorType")) in EncodeFixedType()
306 else if (R->isSubClassOf("LLVMScalarOrSameVectorWidth")) { in EncodeFixedType()
313 else if (R->isSubClassOf("LLVMPointerTo")) in EncodeFixedType()
315 else if (R->isSubClassOf("LLVMVectorOfAnyPointersToElt")) { in EncodeFixedType()
322 } else if (R->isSubClassOf("LLVMPointerToElt")) in EncodeFixedType()
324 else if (R->isSubClassOf("LLVMVectorElementType")) in EncodeFixedType()
326 else if (R->isSubClassOf("LLVMSubdivide2VectorType")) in EncodeFixedType()
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H A DRISCVCompressInstEmitter.cpp142 assert(Reg->isSubClassOf("Register") && "Reg record should be a Register"); in validateRegister()
143 assert(RegClass->isSubClassOf("RegisterClass") && in validateRegister()
161 if (DagOpType->isSubClassOf("RegisterClass") && in validateTypes()
162 InstOpType->isSubClassOf("RegisterClass")) { in validateTypes()
169 if (DagOpType->isSubClassOf("RegisterClass") || in validateTypes()
170 InstOpType->isSubClassOf("RegisterClass")) in validateTypes()
209 if (DI->getDef()->isSubClassOf("Register")) { in addDagOperandMapping()
237 if (Inst.Operands[i].Rec->isSubClassOf("RegisterClass")) in addDagOperandMapping()
420 if (!Operator->isSubClassOf("RVInst")) in evaluateCompressPat()
432 if (!DestOperator->isSubClassOf("RVInst16")) in evaluateCompressPat()
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H A DCodeGenSchedule.cpp481 if (Queue->isSubClassOf("LoadQueue")) { in collectLoadStoreQueueInfo()
492 if (Queue->isSubClassOf("StoreQueue")) { in collectLoadStoreQueueInfo()
547 if (ModelKey->isSubClassOf("SchedMachineModel")) { in addProcModel()
568 if (RWDef->isSubClassOf("WriteSequence")) { in scanSchedRW()
573 else if (RWDef->isSubClassOf("SchedVariant")) { in scanSchedRW()
602 if (RW->isSubClassOf("SchedWrite")) in collectSchedRW()
605 assert(RW->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
616 if (RWDef->isSubClassOf("SchedWrite")) in collectSchedRW()
619 assert(RWDef->isSubClassOf("SchedRead") && "Unknown SchedReadWrite"); in collectSchedRW()
630 if (RWDef->isSubClassOf("SchedWrite")) in collectSchedRW()
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H A DX86FoldTablesEmitter.cpp228 if (RegRec->isSubClassOf("RegisterOperand")) in getRegOperandSize()
230 if (RegRec->isSubClassOf("RegisterClass")) in getRegOperandSize()
238 if (MemRec->isSubClassOf("Operand")) { in getMemOperandSize()
285 return Rec->isSubClassOf("RegisterClass") || in isRegisterOperand()
286 Rec->isSubClassOf("RegisterOperand") || in isRegisterOperand()
287 Rec->isSubClassOf("PointerLikeRegClass"); in isRegisterOperand()
291 return Rec->isSubClassOf("Operand") && in isMemoryOperand()
296 return Rec->isSubClassOf("Operand") && in isImmediateOperand()
588 if (!Inst->TheDef->getNameInit() || !Inst->TheDef->isSubClassOf("X86Inst")) in run()
H A DInstrInfoEmitter.cpp149 if (OpR->isSubClassOf("RegisterOperand")) in GetOperandInfo()
151 if (OpR->isSubClassOf("RegisterClass")) in GetOperandInfo()
153 else if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
163 if (OpR->isSubClassOf("PointerLikeRegClass")) in GetOperandInfo()
168 if (Op.Rec->isSubClassOf("PredicateOp")) in GetOperandInfo()
173 if (Op.Rec->isSubClassOf("OptionalDefOperand")) in GetOperandInfo()
178 if (Op.Rec->isSubClassOf("BranchTargetOperand")) in GetOperandInfo()
433 if ((OpR->isSubClassOf("Operand") || in emitOperandTypeMappings()
434 OpR->isSubClassOf("RegisterOperand") || in emitOperandTypeMappings()
435 OpR->isSubClassOf("RegisterClass")) && in emitOperandTypeMappings()
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H A DFastISelEmitter.cpp265 if (OpLeafRec->isSubClassOf("RegisterOperand")) in initialize()
267 if (OpLeafRec->isSubClassOf("RegisterClass")) in initialize()
269 else if (OpLeafRec->isSubClassOf("Register")) in initialize()
271 else if (OpLeafRec->isSubClassOf("ValueType")) { in initialize()
433 if (!OpLeafRec->isSubClassOf("Register")) in PhyRegForNode()
456 if (!Op->isSubClassOf("Instruction")) in collectPatterns()
475 if (ChildOp->getOperator()->isSubClassOf("Instruction")) { in collectPatterns()
489 if (Op0Rec->isSubClassOf("RegisterOperand")) in collectPatterns()
491 if (!Op0Rec->isSubClassOf("RegisterClass")) in collectPatterns()
H A DSubtargetEmitter.cpp628 if (!PRDef->isSubClassOf("ProcResGroup")) in EmitProcessorResourceSubUnits()
789 if (PRDef->isSubClassOf("ProcResGroup")) { in EmitProcessorResources()
832 if (SchedWrite.TheDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
850 if (AliasDef && AliasDef->isSubClassOf("SchedWriteRes")) in FindWriteResources()
856 if (!WR->isSubClassOf("WriteRes")) in FindWriteResources()
883 if (SchedRead.TheDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()
902 if (AliasDef && AliasDef->isSubClassOf("SchedReadAdvance")) in FindReadAdvance()
908 if (!RA->isSubClassOf("ReadAdvance")) in FindReadAdvance()
939 if (PRDef->isSubClassOf("ProcResGroup")) in ExpandProcResources()
946 if (SubDef->isSubClassOf("ProcResGroup")) { in ExpandProcResources()
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H A DGlobalISelEmitter.cpp283 if (Operator->isSubClassOf("SDNode")) in explainOperator()
286 if (Operator->isSubClassOf("Intrinsic")) in explainOperator()
289 if (Operator->isSubClassOf("ComplexPattern")) in explainOperator()
294 if (Operator->isSubClassOf("SDNodeXForm")) in explainOperator()
380 if (VDefInit->getDef()->isSubClassOf("RegisterOperand")) in getInitValueAsRegClass()
382 if (VDefInit->getDef()->isSubClassOf("RegisterClass")) in getInitValueAsRegClass()
4046 if (!CCDef || !CCDef->isSubClassOf("CondCode")) in createAndImportSelDAGMatcher()
4157 if (ChildRec->isSubClassOf("Register")) { in getSrcChildName()
4175 SrcChild->getOperator()->isSubClassOf("ComplexPattern")) { in importChildMatcher()
4198 if (SrcChild->getOperator()->isSubClassOf("SDNode")) { in importChildMatcher()
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H A DDAGISelEmitter.cpp47 if (Op->isSubClassOf("Instruction")) { in getResultPatternCost()
66 if (Op->isSubClassOf("Instruction")) { in getResultPatternSize()
H A DCodeGenSchedule.h64 IsRead = Def->isSubClassOf("SchedRead"); in CodeGenSchedRW()
65 HasVariants = Def->isSubClassOf("SchedVariant"); in CodeGenSchedRW()
72 IsSequence = Def->isSubClassOf("WriteSequence"); in CodeGenSchedRW()
526 bool IsRead = Def->isSubClassOf("SchedRead"); in getSchedRW()
H A DInfoByHwMode.h164 bool isSubClassOf(const RegSizeInfo &I) const;
177 bool isSubClassOf(const RegSizeInfoByHwMode &I) const;
H A DAsmWriterEmitter.cpp905 if (Rec->isSubClassOf("RegisterOperand") || in EmitPrintAliasInstruction()
906 Rec->isSubClassOf("Operand")) { in EmitPrintAliasInstruction()
921 if (Rec->isSubClassOf("RegisterOperand")) in EmitPrintAliasInstruction()
923 if (Rec->isSubClassOf("RegisterClass")) { in EmitPrintAliasInstruction()
927 if (R->isSubClassOf("RegisterOperand")) in EmitPrintAliasInstruction()
1016 !cast<DefInit>(Arg)->getDef()->isSubClassOf("SubtargetFeature")) in EmitPrintAliasInstruction()
/netbsd-src/external/apache2/llvm/dist/clang/utils/TableGen/
H A DClangSyntaxEmitter.cpp55 assert(N.Record->isSubClassOf("Alternatives") || in Hierarchy()
56 N.Record->isSubClassOf("External") || N.Derived.empty()); in Hierarchy()
57 assert(!N.Record->isSubClassOf("Alternatives") || !N.Derived.empty()); in Hierarchy()
113 if (R.isSubClassOf("Optional")) { in SyntaxConstraint()
115 } else if (R.isSubClassOf("AnyToken")) { in SyntaxConstraint()
117 } else if (R.isSubClassOf("NodeType")) { in SyntaxConstraint()
202 if (N.Record->isSubClassOf("External")) in EmitClangSyntaxNodeClasses()
216 if (N.Record->isSubClassOf("Sequence")) { in EmitClangSyntaxNodeClasses()
219 assert(C->isSubClassOf("Role")); in EmitClangSyntaxNodeClasses()
H A DClangTypeNodesEmitter.cpp155 if (type.isSubClassOf(AlwaysDependentClassName)) in emitNodeInvocations()
157 if (type.isSubClassOf(NeverCanonicalClassName)) in emitNodeInvocations()
159 if (type.isSubClassOf(NeverCanonicalUnlessDependentClassName)) in emitNodeInvocations()
188 if (!type.isSubClassOf(LeafTypeClassName)) continue; in emitLeafNodeInvocations()
H A DASTTableGen.h109 bool isSubClassOf(llvm::StringRef className) const { in isSubClassOf() function
110 return get()->isSubClassOf(className); in isSubClassOf()
115 return (isSubClassOf(NodeClass::getTableGenNodeClassName()) in getAs()
282 if (isSubClassOf(ArrayTypeClassName)) in getArrayElementType()
289 if (isSubClassOf(OptionalTypeClassName)) in getOptionalElementType()
296 if (isSubClassOf(SubclassPropertyTypeClassName)) in getSuperclassType()
310 return isSubClassOf(EnumPropertyTypeClassName); in isEnum()
H A DMveEmitter.cpp1073 if (R->isSubClassOf("Immediate")) in getType()
1075 else if (R->isSubClassOf("unpromoted")) in getType()
1080 if (R->isSubClassOf("PrimitiveType")) in getType()
1082 if (R->isSubClassOf("ComplexType")) in getType()
1093 if (!Op->isSubClassOf("ComplexTypeOp")) in getType()
1119 if (Op->isSubClassOf("CTO_Tuple")) { in getType()
1125 if (Op->isSubClassOf("CTO_Pointer")) { in getType()
1141 if (Op->isSubClassOf("CTO_ScaleSize")) { in getType()
1176 } else if (Op->isSubClassOf("Type")) { in getCodeForDag()
1208 if (!TypeRec->isSubClassOf("Type")) in getCodeForDag()
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H A DClangAttrEmitter.cpp174 if (Attr->isSubClassOf("TargetSpecificAttr") && in getParsedAttrList()
1836 if (Subject.isSubClassOf("DeclNode") || Subject.isSubClassOf("DeclBase") || in isSupportedPragmaClangAttributeSubject()
1840 if (Subject.isSubClassOf("SubsetSubject")) in isSupportedPragmaClangAttributeSubject()
2765 if (Attr->isSubClassOf(TheRecord)) { in classifyAttr()
2934 if (R.isSubClassOf(InhClass)) in EmitClangAttrPCHRead()
2950 if (R.isSubClassOf(InhClass)) in EmitClangAttrPCHRead()
2974 if (R.isSubClassOf(InhClass) || !Args.empty()) in EmitClangAttrPCHWrite()
2977 if (R.isSubClassOf(InhClass)) in EmitClangAttrPCHWrite()
3102 if (Attr->isSubClassOf("TargetSpecificAttr")) { in GenerateHasAttrSpellingStringSwitch()
3502 if (Base->isSubClassOf("SubsetSubject")) { in GenerateCustomAppertainsTo()
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