| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/ |
| H A D | ARMAddressingModes.h | 416 bool isSub = Opc == sub; variable
417 return Imm12 | ((int)isSub << 12) | (SO << 13) | (IdxMode << 16) ;
447 bool isSub = Opc == sub; variable
448 return ((int)isSub << 8) | Offset | (IdxMode << 9);
490 bool isSub = Opc == sub; in getAM5Opc() local
491 return ((int)isSub << 8) | Offset; in getAM5Opc()
511 bool isSub = Opc == sub; in getAM5FP16Opc() local
512 return ((int)isSub << 8) | Offset; in getAM5FP16Opc()
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| H A D | ARMInstPrinter.cpp | 363 bool isSub = OffImm < 0; in printThumbLdrLabelOperand() local
368 if (isSub) { in printThumbLdrLabelOperand()
1191 bool isSub = OffImm < 0; in printAddrModeImm12Operand() local
1195 if (isSub) { in printAddrModeImm12Operand()
1215 bool isSub = OffImm < 0; in printT2AddrModeImm8Operand() local
1219 if (isSub) { in printT2AddrModeImm8Operand()
1244 bool isSub = OffImm < 0; in printT2AddrModeImm8s4Operand() local
1251 if (isSub) { in printT2AddrModeImm8s4Operand()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2InstrInfo.cpp | 289 bool isSub = NumBytes < 0; in emitT2RegPlusImmediate() local
290 if (isSub) NumBytes = -NumBytes; in emitT2RegPlusImmediate()
314 if (isSub) { in emitT2RegPlusImmediate()
357 Opc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitT2RegPlusImmediate()
372 Opc = isSub ? t2SUB : t2ADD; in emitT2RegPlusImmediate()
379 Opc = isSub ? t2SUBi12 : t2ADDi12; in emitT2RegPlusImmediate()
525 bool isSub = false; in rewriteT2FrameIndex() local
557 isSub = true; in rewriteT2FrameIndex()
576 unsigned NewOpc = isSub ? IsSP ? ARM::t2SUBspImm12 : ARM::t2SUBri12 in rewriteT2FrameIndex()
633 isSub = true; in rewriteT2FrameIndex()
[all …]
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| H A D | ThumbRegisterInfo.cpp | 132 bool isSub = false; in emitThumbRegPlusImmInReg() local
138 isSub = true; in emitThumbRegPlusImmInReg()
169 int Opc = (isSub) ? ARM::tSUBrr in emitThumbRegPlusImmInReg()
174 if (DestReg == ARM::SP || isSub) in emitThumbRegPlusImmInReg()
192 bool isSub = NumBytes < 0; in emitThumbRegPlusImmediate() local
194 if (isSub) Bytes = -NumBytes; in emitThumbRegPlusImmediate()
227 ExtraOpc = isSub ? ARM::tSUBspi : ARM::tADDspi; in emitThumbRegPlusImmediate()
233 assert(!isSub && "Thumb1 does not have tSUBrSPi"); in emitThumbRegPlusImmediate()
242 CopyOpc = isSub ? ARM::tSUBi3 : ARM::tADDi3; in emitThumbRegPlusImmediate()
250 ExtraOpc = isSub ? ARM::tSUBi8 : ARM::tADDi8; in emitThumbRegPlusImmediate()
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| H A D | ARMBaseInstrInfo.cpp | 218 bool isSub = ARM_AM::getAM2Op(OffImm) == ARM_AM::sub; in convertToThreeAddress() local
226 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
235 get(isSub ? ARM::SUBrsi : ARM::ADDrsi), WBReg) in convertToThreeAddress()
244 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
252 bool isSub = ARM_AM::getAM3Op(OffImm) == ARM_AM::sub; in convertToThreeAddress() local
257 get(isSub ? ARM::SUBri : ARM::ADDri), WBReg) in convertToThreeAddress()
264 get(isSub ? ARM::SUBrr : ARM::ADDrr), WBReg) in convertToThreeAddress()
2468 bool isSub = NumBytes < 0; in emitARMRegPlusImmediate() local
2469 if (isSub) NumBytes = -NumBytes; in emitARMRegPlusImmediate()
2482 unsigned Opc = isSub ? ARM::SUBri : ARM::ADDri; in emitARMRegPlusImmediate()
[all …]
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| H A D | ARMISelLowering.cpp | 11385 bool isSub = ARM_AM::getAM2Op(Offset) == ARM_AM::sub; in EmitInstrWithCustomInserter() local
11387 if (isSub) in EmitInstrWithCustomInserter()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FrameLowering.cpp | 209 bool isSub = NumBytes < 0; in emitSPUpdate() local
210 uint64_t Offset = isSub ? -NumBytes : NumBytes; in emitSPUpdate()
212 isSub ? MachineInstr::FrameSetup : MachineInstr::FrameDestroy; in emitSPUpdate()
235 if (isSub && !isEAXLiveIn(MBB)) in emitSPUpdate()
242 isSub ? getSUBrrOpcode(Is64Bit) : getADDrrOpcode(Is64Bit); in emitSPUpdate()
266 if (isSub) in emitSPUpdate()
293 unsigned Reg = isSub in emitSPUpdate()
297 unsigned Opc = isSub in emitSPUpdate()
301 .addReg(Reg, getDefRegState(!isSub) | getUndefRegState(isSub)) in emitSPUpdate()
308 BuildStackAdjustment(MBB, MBBI, DL, isSub ? -ThisVal : ThisVal, InEpilogue) in emitSPUpdate()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64InstrFormats.td | 2038 class BaseBaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2047 let Inst{30} = isSub;
2055 class BaseAddSubCarry<bit isSub, RegisterClass regtype, string asm,
2057 : BaseBaseAddSubCarry<isSub, regtype, asm,
2060 class BaseAddSubCarrySetFlags<bit isSub, RegisterClass regtype, string asm,
2062 : BaseBaseAddSubCarry<isSub, regtype, asm,
2068 multiclass AddSubCarry<bit isSub, string asm, string asm_setflags,
2070 def Wr : BaseAddSubCarry<isSub, GPR32, asm, OpNode> {
2074 def Xr : BaseAddSubCarry<isSub, GPR64, asm, OpNode> {
2080 def SWr : BaseAddSubCarrySetFlags<isSub, GPR32, asm_setflags,
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/ |
| H A D | RISCVFrameLowering.cpp | 270 bool isSub = Val < 0; in adjustReg() local
271 if (isSub) { in adjustReg()
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| /netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/ |
| H A D | CGExprScalar.cpp | 3526 bool isSub=false) { in tryEmitFMulAdd() argument
3542 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub); in tryEmitFMulAdd()
3547 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false); in tryEmitFMulAdd()
3554 return buildFMulAdd(LHSBinOp, op.RHS, CGF, Builder, false, isSub); in tryEmitFMulAdd()
3560 return buildFMulAdd(RHSBinOp, op.LHS, CGF, Builder, isSub, false); in tryEmitFMulAdd()
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