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Searched refs:isPredicated (Results 1 – 25 of 47) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonDepInstrInfo.td628 let isPredicated = 1;
644 let isPredicated = 1;
660 let isPredicated = 1;
680 let isPredicated = 1;
701 let isPredicated = 1;
720 let isPredicated = 1;
741 let isPredicated = 1;
756 let isPredicated = 1;
772 let isPredicated = 1;
786 let isPredicated = 1;
[all …]
H A DHexagonVLIWPacketizer.cpp368 return HII->isPredicated(MI) && HII->getDotNewPredOp(MI, nullptr) > 0; in isNewifiable()
570 if (!HII->isPredicated(MI)) in getPredicateSense()
701 if (HII->isPredicated(PacketMI)) { in canPromoteToNewValueStore()
702 if (!HII->isPredicated(MI)) in canPromoteToNewValueStore()
926 if (!HII->isPredicated(*I)) in restrictingDepExistInPacket()
953 assert(QII->isPredicated(MI) && "Must be predicated instruction"); in getPredicatedRegister()
1207 if (HII->isPredicated(I) || HII->isPredicated(J)) in hasDeadDependence()
1247 if (HII->isPredicated(MI) && HII->isPredicatedNew(MI) && HII->isJumpR(MI)) in hasControlDependence()
1468 if (HII->isPredicated(I) && HII->isPredicated(J) && in isLegalToPacketizeTogether()
H A DHexagonInstrFormats.td86 bits<1> isPredicated = 0;
87 let TSFlags{10} = isPredicated;
184 let PredSense = !if(isPredicated, !if(isPredicatedFalse, "false", "true"),
296 bits<1> isPredicated = 0;
297 let TSFlags{7} = isPredicated;
H A DHexagonExpandCondsets.cpp344 if (HII->isPredicated(*DefI)) in updateKillFlags()
422 if (HII->isPredicated(*DefI)) in updateDeadsInRange()
492 if (!HII->isPredicated(*DefI)) in updateDeadsInRange()
724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
759 if (PredValid && HII->isPredicated(*MI)) { in getReachingDefForPred()
917 if (!HII->isPredicated(*MI)) in renameInRange()
990 if (PredValid && HII->isPredicated(*MI) && MI->readsRegister(PredR)) in predicate()
H A DHexagonInstrInfo.h223 bool isPredicated(const MachineInstr &MI) const override;
388 bool isPredicated(unsigned Opcode) const;
H A DHexagonPeephole.cpp235 if (QII->isPredicated(MI)) { in runOnMachineFunction()
H A DHexagon.td320 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
328 let RowFields = ["BaseOpcode", "PNewValue", "PredSense", "isBranch", "isPredicated"];
H A DHexagonInstrInfo.cpp611 if (Term != MBB.end() && isPredicated(*Term) && in insertBranch()
1580 bool HexagonInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in HexagonInstrInfo
2163 if (isNewValueInst(MI) || (isPredicated(MI) && isPredicatedNew(MI))) in isDotNewInst()
2447 return isNewValue(Opcode) && get(Opcode).isBranch() && isPredicated(Opcode); in isNewValueJump()
2470 assert(isPredicated(MI)); in isPredicatedNew()
2476 assert(isPredicated(Opcode)); in isPredicatedNew()
2494 bool HexagonInstrInfo::isPredicated(unsigned Opcode) const { in isPredicated() function in HexagonInstrInfo
3177 if (Cond.empty() || !isPredicated(Cond[0].getImm())) in predOpcodeHasNot()
3242 if (isPredicated(MI)) { in getBaseAndOffsetPosition()
3767 if (isPredicated(NewOp) && isPredicatedNew(NewOp)) { // Get predicate old form in getDotOldOp()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp181 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
213 CantAnalyze = !isPredicated(*I); in analyzeBranch()
221 if (!isPredicated(*I) && (isUncondBranchOpcode(I->getOpcode()) || in analyzeBranch()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp866 bool isPredicated = isVectorPredicated(&MI); in producesFalseLanesZero() local
870 return isPredicated; in producesFalseLanesZero()
894 if (MO.isUse() && isPredicated) in producesFalseLanesZero()
938 bool isPredicated = isVectorPredicated(&MI); in ValidateLiveOuts() local
942 if (isPredicated) in ValidateLiveOuts()
948 else if (!isPredicated && retainsOrReduces) in ValidateLiveOuts()
950 else if (!isPredicated) in ValidateLiveOuts()
H A DARMBaseInstrInfo.cpp361 while (isPredicated(*I) || I->isTerminator() || I->isDebugValue()) { in analyzeBranch()
404 if (!isPredicated(*I) && in analyzeBranch()
433 if (AllowModify && !isPredicated(MBB.back()) && in analyzeBranch()
532 bool ARMBaseInstrInfo::isPredicated(const MachineInstr &MI) const { in isPredicated() function in ARMBaseInstrInfo
2988 if (!isSuitableForMask(MI, SrcReg, CmpMask, false) || isPredicated(*MI)) { in optimizeCompareInstr()
2997 isPredicated(*PotentialAND)) in optimizeCompareInstr()
3116 if (isPredicated(*MI)) in optimizeCompareInstr()
3245 assert(!isPredicated(*MI) && "Can't use flags from predicated instruction"); in optimizeCompareInstr()
3263 if (isPredicated(MI)) in shouldSink()
4931 if (MI.getOpcode() == ARM::VMOVD && !isPredicated(MI)) in getExecutionDomain()
[all …]
H A DARMSchedule.td155 "ARM_MC::isPredicated",
156 "isPredicated"
H A DARMSLSHardening.cpp119 assert(!TII->isPredicated(MI)); in hardenReturnsAndBRs()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DIfConversion.cpp1110 bool isPredicated = TII->isPredicated(MI); in ScanInstructions() local
1122 if (!isPredicated) { in ScanInstructions()
1137 if (BBI.ClobbersPred && !isPredicated) { in ScanInstructions()
1992 bool BB1Predicated = BBI1T != MBB1.end() && TII->isPredicated(*BBI1T); in IfConvertDiamondCommon()
1993 bool BB2NonPredicated = BBI2T != MBB2.end() && !TII->isPredicated(*BBI2T); in IfConvertDiamondCommon()
2084 if (TI != BBI.BB->end() && TII->isPredicated(*TI)) in IfConvertDiamond()
2142 if (I.isDebugInstr() || TII->isPredicated(I)) in PredicateBlock()
2202 if (!TII->isPredicated(I) && !MI->isDebugInstr()) { in CopyAndPredicateBlock()
2256 if (FromTI != FromMBB.end() && !TII->isPredicated(*FromTI)) in MergeBlocks()
H A DCriticalAntiDepBreaker.cpp178 MI.isCall() || MI.hasExtraSrcRegAllocReq() || TII->isPredicated(MI); in PrescanInstruction()
253 if (!TII->isPredicated(MI)) { in ScanInstruction()
608 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI)) in BreakAntiDependencies()
H A DTargetSchedule.cpp306 if (!DepMI->readsRegister(Reg, TRI) && TII->isPredicated(*DepMI)) in computeOutputLatency()
H A DAggressiveAntiDepBreaker.cpp381 if (MI.isCall() || MI.hasExtraDefRegAllocReq() || TII->isPredicated(MI) || in PrescanInstruction()
459 TII->isPredicated(MI) || MI.isInlineAsm(); in ScanInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCInstrInfo.h275 bool isPredicated(MCInstrInfo const &MCII, MCInst const &MCI);
327 bool isPredicated() const;
H A DHexagonMCChecker.cpp68 if (HexagonMCInstrInfo::isPredicated(MCII, MCI) && isPredicateRegister(R)) { in initReg()
435 if (std::get<2>(Producer).isPredicated() && in checkNewValues()
436 (!Consumer.isPredicated() || in checkNewValues()
H A DHexagonMCInstrInfo.cpp35 bool HexagonMCInstrInfo::PredicateInfo::isPredicated() const { in isPredicated() function in HexagonMCInstrInfo::PredicateInfo
718 bool HexagonMCInstrInfo::isPredicated(MCInstrInfo const &MCII, in isPredicated() function in HexagonMCInstrInfo
927 if (!isPredicated(MCII, MCI)) in predicateInfo()
H A DHexagonMCCodeEmitter.cpp759 if (!HexagonMCInstrInfo::isPredicated(MCII, Inst)) { in getMachineOpValue()
763 assert(HexagonMCInstrInfo::isPredicated(MCII, MI) && in getMachineOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMMCTargetDesc.h46 bool isPredicated(const MCInst &MI, const MCInstrInfo *MCII);
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600InstrInfo.h180 bool isPredicated(const MachineInstr &MI) const override;
H A DR600Packetizer.cpp79 if (TII->isPredicated(*BI)) in getPreviousVector()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Analysis/
H A DVectorUtils.cpp1062 (!isPredicated(B->getParent()) || EnablePredicatedInterleavedMemAccesses)) { in analyzeInterleaving()
1164 if ((isPredicated(BlockA) || isPredicated(BlockB)) && in analyzeInterleaving()

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