| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonPseudo.td | 161 let isCall = 1, hasSideEffects = 1, isPredicable = 0,
178 isPredicable = 0 in
207 let isPredicable = 0; // !if(isPred, 0, 1);
220 isPredicable = 1, hasSideEffects = 0, InputType = "reg",
234 isCodeGenOnly = 1, Defs = [PC], Uses = [R28], isPredicable = 0 in
238 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
244 let isPseudo = 1, isCall = 1, isReturn = 1, isBarrier = 1, isPredicable = 0,
337 isPredicable = 1,
353 Defs = [R29, R30, R31, PC], isPredicable = 0, isAsmParserOnly = 1 in {
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| H A D | HexagonExpandCondsets.cpp | 221 bool isPredicable(MachineInstr *MI);
723 bool HexagonExpandCondsets::isPredicable(MachineInstr *MI) { in isPredicable() function in HexagonExpandCondsets
724 if (HII->isPredicated(*MI) || !HII->isPredicable(*MI)) in isPredicable()
961 if (!DefI || !isPredicable(DefI)) in predicate()
1228 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
1239 if (!RDef || !HII->isPredicable(*RDef)) { in coalesceSegments()
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| H A D | HexagonEarlyIfConv.cpp | 482 if (!HII->isPredicable(*Def1) || !HII->isPredicable(*Def3)) in computePhiCost()
681 return MI->mayStore() && HII->isPredicable(const_cast<MachineInstr&>(*MI)); in isPredicableStore()
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| H A D | HexagonDepInstrInfo.td | 57 let isPredicable = 1;
221 let isPredicable = 1;
307 let isPredicable = 1;
345 let isPredicable = 1;
357 let isPredicable = 1;
432 let isPredicable = 1;
592 let isPredicable = 1;
1068 let isPredicable = 1;
1403 let isPredicable = 1;
1415 let isPredicable = 1;
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| H A D | HexagonInstrInfo.h | 247 bool isPredicable(const MachineInstr &MI) const override;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/MC/ |
| H A D | MCInstrDesc.h | 329 bool isPredicable() const { return Flags & (1ULL << MCID::Predicable); } in isPredicable() function
622 if (isPredicable()) { in findFirstPredOperandIdx()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | Thumb2SizeReduction.cpp | 806 if (!NewMCID.isPredicable()) in ReduceTo2Addr()
810 SkipPred = !NewMCID.isPredicable(); in ReduceTo2Addr()
899 if (!NewMCID.isPredicable()) in ReduceToNarrow()
903 SkipPred = !NewMCID.isPredicable(); in ReduceToNarrow()
968 if (!MCID.isPredicable() && NewMCID.isPredicable()) in ReduceToNarrow()
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| H A D | ARMInstrCDE.td | 65 let isPredicable = 0;
77 let isPredicable = acc;
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| H A D | ThumbRegisterInfo.cpp | 561 if (MI.isPredicable()) in eliminateFrameIndex()
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| H A D | ARMConstantIslandPass.cpp | 623 MI->getOperand(NumOps - (MI->isPredicable() ? 2 : 1)); in doInitialJumpTablePlacement()
2185 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1); in optimizeThumb2JumpTables()
2379 unsigned JTOpIdx = NumOps - (MI->isPredicable() ? 2 : 1); in reorderThumb2JumpTables()
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| H A D | ARMBaseInstrInfo.h | 181 bool isPredicable(const MachineInstr &MI) const override;
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | CodeGenInstruction.h | 152 bool isPredicable; variable
256 bool isPredicable : 1; variable
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| H A D | CodeGenInstruction.cpp | 28 isPredicable = false; in CGIOperandList()
109 isPredicable = true; in CGIOperandList()
385 isPredicable = !R->getValueAsBit("isUnpredicable") && ( in CodeGenInstruction()
386 Operands.isPredicable || R->getValueAsBit("isPredicable")); in CodeGenInstruction()
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| H A D | InstrDocsEmitter.cpp | 118 FLAG(isPredicable) in EmitInstrDocs()
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| H A D | InstrInfoEmitter.cpp | 964 if (Inst.isPredicable) OS << "|(1ULL<<MCID::Predicable)"; in emitRecord()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 182 bool isPredicable(const MachineInstr &MI) const override;
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| H A D | R600InstrInfo.cpp | 854 bool R600InstrInfo::isPredicable(const MachineInstr &MI) const { in isPredicable() function in R600InstrInfo
872 return TargetInstrInfo::isPredicable(MI); in isPredicable()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/ |
| H A D | SystemZInstrInfo.h | 247 bool isPredicable(const MachineInstr &MI) const override;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/CSKY/ |
| H A D | CSKYInstrInfo.td | 307 let isBarrier = 1, isPredicable = 1 in
346 let isPredicable = 1;
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1471 virtual bool isPredicable(const MachineInstr &MI) const { in isPredicable() function
1472 return MI.getDesc().isPredicable(); in isPredicable()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | ImplicitNullChecks.cpp | 374 if (!MI.mayLoadOrStore() || MI.isPredicable()) in isSuitableMemoryOp()
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| H A D | TargetInstrInfo.cpp | 326 if (!MI.isPredicable()) in isUnpredicatedTerminator()
339 if (!MI.isPredicable()) in PredicateInstruction()
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| H A D | EarlyIfConversion.cpp | 328 if (!TII->isPredicable(*I) || TII->isPredicated(*I)) { in canPredicateInstrs()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/ |
| H A D | LanaiInstrInfo.cpp | 467 if (!MI->isPredicable()) in canFoldIntoSelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/docs/TableGen/ |
| H A D | index.rst | 127 bit isPredicable = 0;
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