| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86RegisterBankInfo.h | 35 static PartialMappingIdx getPartialMappingIdx(const LLT &Ty, bool isFP);
49 bool isFP) const;
54 const MachineRegisterInfo &MRI, const bool isFP,
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| H A D | X86RegisterBankInfo.cpp | 66 X86GenRegisterBankInfo::getPartialMappingIdx(const LLT &Ty, bool isFP) { in getPartialMappingIdx() argument
67 if ((Ty.isScalar() && !isFP) || Ty.isPointer()) { in getPartialMappingIdx()
112 const MachineInstr &MI, const MachineRegisterInfo &MRI, const bool isFP, in getInstrPartialMappingIdxs() argument
121 OpRegBankIdx[Idx] = getPartialMappingIdx(MRI.getType(MO.getReg()), isFP); in getInstrPartialMappingIdxs()
146 bool isFP) const { in getSameOperandsMapping()
157 auto Mapping = getValueMapping(getPartialMappingIdx(Ty, isFP), 3); in getSameOperandsMapping()
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| H A D | X86ISelLowering.cpp | 5029 bool isFP, SDValue &LHS, SDValue &RHS, in TranslateX86CC() argument
5031 if (!isFP) { in TranslateX86CC()
22897 bool isFP = Op1.getSimpleValueType().isFloatingPoint(); in LowerVSETCC() local
22900 if (isFP) { in LowerVSETCC()
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| /netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/ |
| H A D | FastISelEmitter.cpp | 107 bool isFP() const { return Repr == OK_FP; } in isFP() function in __anon2f99e1bb0311::OperandsSignature::OpKind
116 else if (isFP()) in printManglingSuffix()
300 } else if (Operands[i].isFP()) { in PrintParameters()
322 } else if (Operands[i].isFP()) { in PrintArguments()
338 } else if (Operands[i].isFP()) { in PrintArguments()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | FLATInstructions.td | 377 bit isFP = isFloatType<data_vt>.ret,
386 let FPAtomic = isFP;
398 let FPAtomic = isFP;
410 bit isFP = isFloatType<data_vt>.ret,
421 let FPAtomic = isFP;
433 let FPAtomic = isFP;
444 bit isFP = isFloatType<data_vt>.ret,
457 let FPAtomic = isFP;
469 let FPAtomic = isFP;
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| H A D | BUFInstructions.td | 733 bit isFP = isFloatType<vdataType>.ret> {
734 let FPAtomic = isFP in
738 let FPAtomic = isFP in
742 let FPAtomic = isFP in
745 let FPAtomic = isFP in
749 let FPAtomic = isFP in
757 bit isFP = isFloatType<vdataType>.ret> {
758 let FPAtomic = isFP in
765 let FPAtomic = isFP in
772 let FPAtomic = isFP in
[all …]
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| H A D | SIInstrInfo.td | 1456 bit isFP = isFloatType<VT>.ret;
1459 !if(isFP,
1500 bit isFP = isFloatType<VT>.ret;
1503 RegisterOperand ret = !if(isFP, retFlt, retInt);
1509 bit isFP = isFloatType<VT>.ret;
1514 !if(isFP,
1523 !if(isFP,
1560 bit isFP = isFloatType<VT>.ret;
1563 !if(isFP, FP64InputMods, Int64InputMods),
1564 !if(isFP,
[all …]
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| H A D | MIMGInstructions.td | 582 bit isFP = 0> {
585 ssamp = 0, FPAtomic = isFP in {
640 multiclass MIMG_Atomic <mimgopc op, string asm, bit isCmpSwap = 0, bit isFP = 0> { // 64-bit atomics
652 defm _V1 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_64, VGPR_32), 1, isFP>;
654 defm _V2 : MIMG_Atomic_Addr_Helper_m <op, asm, !if(isCmpSwap, VReg_128, VReg_64), 0, isFP>;
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrFormats.td | 146 bits<1> isFP = 0;
147 let TSFlags {50} = isFP; // Floating-point.
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| H A D | HexagonDepInstrInfo.td | 4117 let isFP = 1;
4129 let isFP = 1;
4139 let isFP = 1;
4149 let isFP = 1;
4161 let isFP = 1;
4171 let isFP = 1;
4181 let isFP = 1;
4193 let isFP = 1;
4205 let isFP = 1;
4217 let isFP = 1;
[all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/ |
| H A D | AArch64InstructionSelector.cpp | 2347 const bool isFP = Opcode == TargetOpcode::G_FCONSTANT; in select() local
2362 if (isFP) { in select()
2404 if (isFP) { in select()
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