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Searched refs:isBeforeLegalizeOps (Results 1 – 12 of 12) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DTargetLowering.cpp605 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedBits()
2313 !DCI.isBeforeLegalizeOps()); in SimplifyDemandedVectorElts()
3175 if (DCI.isBeforeLegalizeOps() || in foldSetCCWithAnd()
3501 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3510 (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3739 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3792 if (DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3910 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3930 if ((DCI.isBeforeLegalizeOps() || in SimplifySetCC()
3946 if (!VT.isVector() || DCI.isBeforeLegalizeOps()) { in SimplifySetCC()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsISelLowering.cpp568 if (DCI.isBeforeLegalizeOps()) in performDivRemCombine()
677 if (DCI.isBeforeLegalizeOps()) in performSELECTCombine()
758 if (DCI.isBeforeLegalizeOps()) in performCMovFPCombine()
785 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performANDCombine()
871 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasExtractInsert()) in performORCombine()
1059 if (DCI.isBeforeLegalizeOps()) { in performSUBCombine()
1074 if (DCI.isBeforeLegalizeOps()) { in performADDCombine()
1109 if (DCI.isBeforeLegalizeOps() || !Subtarget.hasCnMips()) in performSHLCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelLowering.cpp1607 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
1623 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ISelLowering.cpp11990 if (DCI.isBeforeLegalizeOps()) in performXorCombine()
12203 if (DCI.isBeforeLegalizeOps()) in performMulCombine()
12447 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFpToIntCombine()
12450 assert((ResTy != MVT::v4i64 || DCI.isBeforeLegalizeOps()) && in performFpToIntCombine()
12520 if (ResTy == MVT::v4i64 && DCI.isBeforeLegalizeOps()) in performFDivCombine()
12738 if (DCI.isBeforeLegalizeOps()) in performSVEAndCombine()
13080 if (DCI.isBeforeLegalizeOps()) in performConcatVectorsCombine()
13172 if (DCI.isBeforeLegalizeOps()) in tryCombineFixedPointConvert()
13482 if (DCI.isBeforeLegalizeOps()) in performAddSubLongCombine()
13543 if (DCI.isBeforeLegalizeOps()) in tryCombineLongOpWithDup()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86ISelLowering.cpp37713 if (!DCI.isBeforeLegalizeOps() && N0.hasOneUse()) { in combineTargetShuffle()
39715 if (!DCI.isBeforeLegalizeOps()) in combineCastedMaskArithmetic()
40548 if (DCI.isBeforeLegalizeOps()) in combineExtractWithShuffle()
41401 !DCI.isBeforeLegalizeOps()); in combineVSelectToBLENDV()
41524 if (CondConstantVector && DCI.isBeforeLegalizeOps()) { in combineSelect()
42689 if (!DCI.isBeforeLegalize() && !DCI.isBeforeLegalizeOps()) { in combineCMov()
44568 if (DCI.isBeforeLegalizeOps()) in combineAnd()
44933 if (DCI.isBeforeLegalizeOps()) in combineOr()
45444 if (RegVT.is256BitVector() && !DCI.isBeforeLegalizeOps() && in combineLoad()
45941 St->getValue().hasOneUse() && !DCI.isBeforeLegalizeOps()) { in combineStore()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetLowering.h3510 bool isBeforeLegalizeOps() const { return Level < AfterLegalizeVectorOps; } in isBeforeLegalizeOps() function
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ISelLowering.cpp1903 if (DCI.isBeforeLegalizeOps() || in PerformDAGCombine()
H A DAMDGPUISelLowering.cpp4070 !DCI.isBeforeLegalizeOps()); in PerformDAGCombine()
H A DSIISelLowering.cpp9286 if (VT != MVT::i64 || DCI.isBeforeLegalizeOps()) in performOrCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonISelLoweringHVX.cpp2239 if (DCI.isBeforeLegalizeOps()) in PerformHvxDAGCombine()
H A DHexagonISelLowering.cpp3238 if (DCI.isBeforeLegalizeOps()) in PerformDAGCombine()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCISelLowering.cpp16826 bool LegalOps = !DCI.isBeforeLegalizeOps(); in combineFMALike()