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/netbsd-src/external/gpl3/gdb/dist/sim/testsuite/m32r/
H A DChangeLog-202173 * bnc24.cgs: Test long BNC instruction.
74 * bnc8.cgs: Test short BNC instruction.
75 * ld-plus.cgs: Test LD instruction.
76 * macwhi.cgs: Test MACWHI instruction.
77 * macwlo.cgs: Test MACWLO instruction.
78 * mulwhi.cgs: Test MULWHI instruction.
79 * mulwlo.cgs: Test MULWLO instruction.
80 * mvfachi.cgs: Test MVFACHI instruction.
81 * mvfaclo.cgs: Test MVFACLO instruction.
82 * mvtaclo.cgs: Test MVTACLO instruction.
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/nios2/
H A Dnios2.opt102 Floating point custom instruction configuration name.
106 Do not use the ftruncds custom instruction.
110 Integer id (N) of ftruncds custom instruction.
114 Do not use the fextsd custom instruction.
118 Integer id (N) of fextsd custom instruction.
122 Do not use the fixdu custom instruction.
126 Integer id (N) of fixdu custom instruction.
130 Do not use the fixdi custom instruction.
134 Integer id (N) of fixdi custom instruction.
138 Do not use the fixsu custom instruction.
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/nios2/
H A Dnios2.opt102 Floating point custom instruction configuration name.
106 Do not use the ftruncds custom instruction.
110 Integer id (N) of ftruncds custom instruction.
114 Do not use the fextsd custom instruction.
118 Integer id (N) of fextsd custom instruction.
122 Do not use the fixdu custom instruction.
126 Integer id (N) of fixdu custom instruction.
130 Do not use the fixdi custom instruction.
134 Integer id (N) of fixdi custom instruction.
138 Do not use the fixsu custom instruction.
[all …]
/netbsd-src/external/gpl3/binutils/dist/opcodes/
H A Dtic4x-dis.c355 unsigned long instruction, in tic4x_print_op() argument
370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16))) in tic4x_print_op()
374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23))) in tic4x_print_op()
398 EXTRU (instruction, 15, 0))) in tic4x_print_op()
403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); in tic4x_print_op()
407 tic4x_print_direct (info, EXTRU (instruction, 15, 0)); in tic4x_print_op()
411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) + in tic4x_print_op()
419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0), in tic4x_print_op()
422 tic4x_print_addr (info, EXTRU (instruction, 23, 0)); in tic4x_print_op()
429 EXTRU (instruction, 7, 0))) in tic4x_print_op()
[all …]
H A Dcr16-dis.c75 static const inst *instruction; variable
124 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) in get_number_of_operands()
296 unsigned long mask = SBM (instruction->match_bits); in build_mask()
299 if ((IS_INSN_MNEMONIC("b") && instruction->size == 2)) in build_mask()
315 instruction = &cr16_instruction[NUMOPCODES - 2]; in cr16_match_opcode()
318 while (instruction >= cr16_instruction) in cr16_match_opcode()
322 if ((doubleWord & mask) == BIN (instruction->match, in cr16_match_opcode()
323 instruction->match_bits)) in cr16_match_opcode()
326 instruction--; in cr16_match_opcode()
339 if ((instruction->size == 3) && a->size >= 16) in make_argument()
[all …]
H A Dcrx-dis.c85 static const inst *instruction; variable
108 for (i = 0; i < MAX_OPERANDS && instruction->operands[i].op_type; i++) in get_number_of_operands()
306 print_flags = instruction->flags & FMT_CRX; in build_mask()
325 mask = SBM(instruction->match_bits); in build_mask()
343 instruction = &crx_instruction[NUMOPCODES - 2]; in match_opcode()
346 while (instruction >= crx_instruction) in match_opcode()
349 if ((doubleWord & mask) == BIN(instruction->match, instruction->match_bits)) in match_opcode()
352 instruction--; in match_opcode()
365 if ((instruction->size == 3) && a->size >= 16) in make_argument()
461 if (instruction->flags & DISPUW4) in make_argument()
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/opcodes/
H A Dtic4x-dis.c355 unsigned long instruction, in tic4x_print_op() argument
370 if (! tic4x_print_cond (info, EXTRU (instruction, 20, 16))) in tic4x_print_op()
374 if (! tic4x_print_cond (info, EXTRU (instruction, 27, 23))) in tic4x_print_op()
398 EXTRU (instruction, 15, 0))) in tic4x_print_op()
403 tic4x_print_immed (info, IMMED_UINT, EXTRU (instruction, 15, 0)); in tic4x_print_op()
407 tic4x_print_direct (info, EXTRU (instruction, 15, 0)); in tic4x_print_op()
411 if (! tic4x_print_register (info, EXTRU (instruction, 24, 22) + in tic4x_print_op()
419 tic4x_print_relative (info, pc, EXTRS (instruction, 23, 0), in tic4x_print_op()
422 tic4x_print_addr (info, EXTRU (instruction, 23, 0)); in tic4x_print_op()
429 EXTRU (instruction, 7, 0))) in tic4x_print_op()
[all …]
H A Dcr16-dis.c75 static const inst *instruction; variable
124 for (i = 0; instruction->operands[i].op_type && i < MAX_OPERANDS; i++) in get_number_of_operands()
296 unsigned long mask = SBM (instruction->match_bits); in build_mask()
299 if ((IS_INSN_MNEMONIC("b") && instruction->size == 2)) in build_mask()
315 instruction = &cr16_instruction[NUMOPCODES - 2]; in cr16_match_opcode()
318 while (instruction >= cr16_instruction) in cr16_match_opcode()
322 if ((doubleWord & mask) == BIN (instruction->match, in cr16_match_opcode()
323 instruction->match_bits)) in cr16_match_opcode()
326 instruction--; in cr16_match_opcode()
339 if ((instruction->size == 3) && a->size >= 16) in make_argument()
[all …]
H A Dcrx-dis.c85 static const inst *instruction; variable
108 for (i = 0; i < MAX_OPERANDS && instruction->operands[i].op_type; i++) in get_number_of_operands()
306 print_flags = instruction->flags & FMT_CRX; in build_mask()
325 mask = SBM(instruction->match_bits); in build_mask()
343 instruction = &crx_instruction[NUMOPCODES - 2]; in match_opcode()
346 while (instruction >= crx_instruction) in match_opcode()
349 if ((doubleWord & mask) == BIN(instruction->match, instruction->match_bits)) in match_opcode()
352 instruction--; in match_opcode()
365 if ((instruction->size == 3) && a->size >= 16) in make_argument()
461 if (instruction->flags & DISPUW4) in make_argument()
[all …]
/netbsd-src/external/gpl3/gdb.old/dist/sim/ppc/
H A Dgen-semantics.c68 insn *instruction, in print_semantic_declaration() argument
74 instruction->file_entry->fields[insn_name], in print_semantic_declaration()
80 instruction->file_entry->fields[insn_name], in print_semantic_declaration()
106 insn *instruction, in print_semantic_body() argument
110 print_itrace(file, instruction->file_entry, 0/*put_value_in_cache*/); in print_semantic_body()
114 print_idecode_validate(file, instruction, opcodes); in print_semantic_body()
123 instruction->file_entry->fields[insn_name], in print_semantic_body()
133 if (instruction->file_entry->annex != NULL) { in print_semantic_body()
135 table_entry_print_cpp_line_nr(file, instruction->file_entry); in print_semantic_body()
138 lf_print__c_code(file, instruction->file_entry->annex); in print_semantic_body()
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/gas/config/
H A Dtc-score7.c447 unsigned long instruction; member
1170 s7_inst.instruction |= reg << shift; in s7_reg_required_here()
1226 if ((((s7_inst.instruction >> 15) & 0x10) == 0) in s7_do_rdrsrs()
1227 && (((s7_inst.instruction >> 10) & 0x10) == 0) in s7_do_rdrsrs()
1228 && (((s7_inst.instruction >> 20) & 0x10) == 0) in s7_do_rdrsrs()
1230 && (((s7_inst.instruction >> 20) & 0xf) == ((s7_inst.instruction >> 15) & 0xf))) in s7_do_rdrsrs()
1232 s7_inst.relax_inst |= (((s7_inst.instruction >> 10) & 0xf) << 4) in s7_do_rdrsrs()
1233 | (((s7_inst.instruction >> 15) & 0xf) << 8); in s7_do_rdrsrs()
1613 s7_inst.instruction |= 0x8000000; in s7_data_op2()
1614 s7_inst.instruction |= ((s7_inst.reloc.exp.X_add_number >> 16) << 1) & 0x1fffe; in s7_data_op2()
[all …]
H A Dtc-arm.c521 unsigned long instruction; member
7432 || ((inst.instruction & 0xf0) == 0x60 \ in parse_operands()
8324 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900; in do_scalar_fp16_v82_encode()
8402 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); in encode_arm_vfp_reg()
8406 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); in encode_arm_vfp_reg()
8410 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); in encode_arm_vfp_reg()
8414 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); in encode_arm_vfp_reg()
8418 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); in encode_arm_vfp_reg()
8422 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); in encode_arm_vfp_reg()
8454 inst.instruction |= SHIFT_ROR << 5; in encode_arm_shift()
[all …]
H A Dtc-score.c385 bfd_vma instruction; member
1086 s3_inst.instruction |= (bfd_vma) reg << shift; in s3_reg_required_here()
1144 if (((s3_inst.instruction & 0x3e0003ff) == 0x00000340 in s3_do_rdrsrs()
1145 || (s3_inst.instruction & 0x3e0003ff) == 0x00000342) in s3_do_rdrsrs()
1152 if ((((s3_inst.instruction >> 15) & 0x10) == 0) in s3_do_rdrsrs()
1153 && (((s3_inst.instruction >> 10) & 0x10) == 0) in s3_do_rdrsrs()
1154 && (((s3_inst.instruction >> 20) & 0x10) == 0) in s3_do_rdrsrs()
1156 && (((s3_inst.instruction >> 20) & 0xf) == ((s3_inst.instruction >> 15) & 0xf))) in s3_do_rdrsrs()
1158 s3_inst.relax_inst |= (((s3_inst.instruction >> 10) & 0xf) ) in s3_do_rdrsrs()
1159 | (((s3_inst.instruction >> 15) & 0xf) << 4); in s3_do_rdrsrs()
[all …]
H A Dtc-s12z.c782 struct instruction;
784 typedef bool (*parse_operand_func) (const struct instruction *);
786 struct instruction struct
807 no_operands (const struct instruction *insn) in no_operands() argument
869 opr (const struct instruction *insn) in opr()
983 rel (const struct instruction *insn) in rel()
998 reg_inh (const struct instruction *insn) in reg_inh()
1017 clr_xy (const struct instruction *insn ATTRIBUTE_UNUSED) in clr_xy()
1033 size_from_suffix (const struct instruction *insn, int idx) in size_from_suffix()
1063 mul_reg_reg_reg (const struct instruction *insn) in mul_reg_reg_reg()
[all …]
/netbsd-src/external/gpl3/binutils/dist/gas/config/
H A Dtc-score7.c447 unsigned long instruction; member
1170 s7_inst.instruction |= reg << shift; in s7_reg_required_here()
1226 if ((((s7_inst.instruction >> 15) & 0x10) == 0) in s7_do_rdrsrs()
1227 && (((s7_inst.instruction >> 10) & 0x10) == 0) in s7_do_rdrsrs()
1228 && (((s7_inst.instruction >> 20) & 0x10) == 0) in s7_do_rdrsrs()
1230 && (((s7_inst.instruction >> 20) & 0xf) == ((s7_inst.instruction >> 15) & 0xf))) in s7_do_rdrsrs()
1232 s7_inst.relax_inst |= (((s7_inst.instruction >> 10) & 0xf) << 4) in s7_do_rdrsrs()
1233 | (((s7_inst.instruction >> 15) & 0xf) << 8); in s7_do_rdrsrs()
1613 s7_inst.instruction |= 0x8000000; in s7_data_op2()
1614 s7_inst.instruction |= ((s7_inst.reloc.exp.X_add_number >> 16) << 1) & 0x1fffe; in s7_data_op2()
[all …]
H A Dtc-arm.c521 unsigned long instruction; member
7462 || ((inst.instruction & 0xf0) == 0x60 \ in parse_operands()
8354 inst.instruction = (inst.instruction & 0xfffff0ff) | 0x900; in do_scalar_fp16_v82_encode()
8432 inst.instruction |= ((reg >> 1) << 12) | ((reg & 1) << 22); in encode_arm_vfp_reg()
8436 inst.instruction |= ((reg >> 1) << 16) | ((reg & 1) << 7); in encode_arm_vfp_reg()
8440 inst.instruction |= ((reg >> 1) << 0) | ((reg & 1) << 5); in encode_arm_vfp_reg()
8444 inst.instruction |= ((reg & 15) << 12) | ((reg >> 4) << 22); in encode_arm_vfp_reg()
8448 inst.instruction |= ((reg & 15) << 16) | ((reg >> 4) << 7); in encode_arm_vfp_reg()
8452 inst.instruction |= (reg & 15) | ((reg >> 4) << 5); in encode_arm_vfp_reg()
8484 inst.instruction |= SHIFT_ROR << 5; in encode_arm_shift()
[all …]
H A Dtc-score.c381 bfd_vma instruction; member
1082 s3_inst.instruction |= (bfd_vma) reg << shift; in s3_reg_required_here()
1140 if (((s3_inst.instruction & 0x3e0003ff) == 0x00000340 in s3_do_rdrsrs()
1141 || (s3_inst.instruction & 0x3e0003ff) == 0x00000342) in s3_do_rdrsrs()
1148 if ((((s3_inst.instruction >> 15) & 0x10) == 0) in s3_do_rdrsrs()
1149 && (((s3_inst.instruction >> 10) & 0x10) == 0) in s3_do_rdrsrs()
1150 && (((s3_inst.instruction >> 20) & 0x10) == 0) in s3_do_rdrsrs()
1152 && (((s3_inst.instruction >> 20) & 0xf) == ((s3_inst.instruction >> 15) & 0xf))) in s3_do_rdrsrs()
1154 s3_inst.relax_inst |= (((s3_inst.instruction >> 10) & 0xf) ) in s3_do_rdrsrs()
1155 | (((s3_inst.instruction >> 15) & 0xf) << 4); in s3_do_rdrsrs()
[all …]
H A Dtc-s12z.c782 struct instruction;
784 typedef bool (*parse_operand_func) (const struct instruction *);
786 struct instruction struct
807 no_operands (const struct instruction *insn) in no_operands() argument
869 opr (const struct instruction *insn) in opr()
983 rel (const struct instruction *insn) in rel()
998 reg_inh (const struct instruction *insn) in reg_inh()
1017 clr_xy (const struct instruction *insn ATTRIBUTE_UNUSED) in clr_xy()
1033 size_from_suffix (const struct instruction *insn, int idx) in size_from_suffix()
1063 mul_reg_reg_reg (const struct instruction *insn) in mul_reg_reg_reg()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Support/
H A DTargetOpcodes.def9 // This file defines the target independent instruction opcodes.
27 /// Every instruction defined here must also appear in Target.td.
37 /// KILL - This instruction is a noop that is used only to adjust the
42 /// EXTRACT_SUBREG - This instruction takes two operands: a register
48 /// INSERT_SUBREG - This instruction takes three operands: a register that
60 /// The result of this instruction is the value of the second operand inserted
63 /// first operand. This instruction just communicates information; No code
65 /// This is typically used after an instruction where the write to a subregister
69 /// COPY_TO_REGCLASS - This instruction is a placeholder for a plain
71 /// used between instruction selection and MachineInstr creation, before
[all …]
/netbsd-src/external/gpl3/gcc/dist/gcc/config/arm/
H A Dunspecs.md36 ; that points at the containing instruction.
45 UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
46 UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction.
47 UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
48 UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction.
49 UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
50 UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction.
51 UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction.
52 UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
53 UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
[all …]
/netbsd-src/external/gpl3/binutils/dist/gas/doc/
H A Dc-d30v.texi37 time it adds a nop instruction.
42 multiply instruction.
67 The D30V version of @code{@value{AS}} uses the instruction names in the D30V
69 There are instruction names that can assemble to a short or long form opcode.
73 assembler to use either the short or long form of the instruction, you can append
87 into a single instruction. The assembler will do this automatically. It will also detect
89 instruction will never be packaged with the previous one. Whenever a branch and link
90 instruction is called, it will not be packaged with the next instruction so the return
109 @cindex sub-instruction ordering, D30V
110 @cindex D30V sub-instruction ordering
[all …]
H A Dc-s390.texi77 Assembling an instruction that is not supported on the target
128 @cindex instruction syntax, s390
129 @cindex s390 instruction syntax
135 Each instruction has two major parts, the instruction mnemonic
136 and the instruction operands. The instruction format varies.
156 instruction formats is an unsigned integer between 0 and 15. The specific
157 instruction and the position of the register in the instruction format
174 @cindex instruction mnemonics, s390
175 @cindex s390 instruction mnemonics
179 The instruction mnemonic identifies the instruction format
[all …]
/netbsd-src/external/gpl3/binutils.old/dist/gas/doc/
H A Dc-d30v.texi37 time it adds a nop instruction.
42 multiply instruction.
67 The D30V version of @code{@value{AS}} uses the instruction names in the D30V
69 There are instruction names that can assemble to a short or long form opcode.
73 assembler to use either the short or long form of the instruction, you can append
87 into a single instruction. The assembler will do this automatically. It will also detect
89 instruction will never be packaged with the previous one. Whenever a branch and link
90 instruction is called, it will not be packaged with the next instruction so the return
109 @cindex sub-instruction ordering, D30V
110 @cindex D30V sub-instruction ordering
[all …]
/netbsd-src/external/gpl3/gcc.old/dist/gcc/config/arm/
H A Dunspecs.md36 ; that points at the containing instruction.
45 UNSPEC_WSHUFH ; Used by the intrinsic form of the iWMMXt WSHUFH instruction.
46 UNSPEC_WACC ; Used by the intrinsic form of the iWMMXt WACC instruction.
47 UNSPEC_TMOVMSK ; Used by the intrinsic form of the iWMMXt TMOVMSK instruction.
48 UNSPEC_WSAD ; Used by the intrinsic form of the iWMMXt WSAD instruction.
49 UNSPEC_WSADZ ; Used by the intrinsic form of the iWMMXt WSADZ instruction.
50 UNSPEC_WMACS ; Used by the intrinsic form of the iWMMXt WMACS instruction.
51 UNSPEC_WMACU ; Used by the intrinsic form of the iWMMXt WMACU instruction.
52 UNSPEC_WMACSZ ; Used by the intrinsic form of the iWMMXt WMACSZ instruction.
53 UNSPEC_WMACUZ ; Used by the intrinsic form of the iWMMXt WMACUZ instruction.
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/bindings/ocaml/llvm/
H A Dllvm.mli59 (** The kind id of metadata attached to an instruction. *)
160 (** The predicate for an integer comparison ([icmp]) instruction.
176 (** The predicate for a floating-point comparison ([fcmp]) instruction.
203 | Invalid (** Not an instruction *)
280 (** The type of a clause of a [landingpad] instruction.
301 [fence] instruction. See [llvm::AtomicOrdering]. *)
314 (** The opcode of an [atomicrmw] instruction.
855 instruction [i].
904 (** [has_metadata i] returns whether or not the instruction [i] has any
910 kind [kind] in the instruction [i] See the function
[all …]

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