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Searched refs:hasSubClassEq (Results 1 – 25 of 37) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVInstrInfo.cpp257 if (RISCV::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
261 } else if (RISCV::FPR16RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
264 } else if (RISCV::FPR32RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
267 } else if (RISCV::FPR64RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
270 } else if (RISCV::VRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
273 } else if (RISCV::VRM2RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
276 } else if (RISCV::VRM4RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
279 } else if (RISCV::VRM8RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
282 } else if (RISCV::VRN2M1RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
284 else if (RISCV::VRN2M2RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86RegisterBankInfo.cpp47 if (X86::GR8RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
48 X86::GR16RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
49 X86::GR32RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
50 X86::GR64RegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
51 X86::LOW32_ADDR_ACCESSRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
52 X86::LOW32_ADDR_ACCESS_RBPRegClass.hasSubClassEq(&RC)) in getRegBankFromRegClass()
55 if (X86::FR32XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
56 X86::FR64XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
57 X86::VR128XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
58 X86::VR256XRegClass.hasSubClassEq(&RC) || in getRegBankFromRegClass()
[all …]
H A DX86DomainReassignment.cpp45 return X86::GR64RegClass.hasSubClassEq(RC) || in isGPR()
46 X86::GR32RegClass.hasSubClassEq(RC) || in isGPR()
47 X86::GR16RegClass.hasSubClassEq(RC) || in isGPR()
48 X86::GR8RegClass.hasSubClassEq(RC); in isGPR()
53 return X86::VK16RegClass.hasSubClassEq(RC); in isMask()
69 if (X86::GR8RegClass.hasSubClassEq(SrcRC)) in getDstRC()
71 if (X86::GR16RegClass.hasSubClassEq(SrcRC)) in getDstRC()
73 if (X86::GR32RegClass.hasSubClassEq(SrcRC)) in getDstRC()
75 if (X86::GR64RegClass.hasSubClassEq(SrcRC)) in getDstRC()
H A DX86InstrInfo.cpp3328 if (X86::GR16RegClass.hasSubClassEq(RC) || in canInsertSelect()
3329 X86::GR32RegClass.hasSubClassEq(RC) || in canInsertSelect()
3330 X86::GR64RegClass.hasSubClassEq(RC)) { in canInsertSelect()
3546 assert(X86::GR8RegClass.hasSubClassEq(RC) && "Unknown 1-byte regclass"); in getLoadStoreRegOpcode()
3550 if (isHReg(Reg) || X86::GR8_ABCD_HRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3554 if (X86::VK16RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3556 assert(X86::GR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
3559 if (X86::GR32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3561 if (X86::FR32XRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
3569 if (X86::RFP32RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEInstrInfo.cpp254 if (Mips::GPR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
256 else if (Mips::GPR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
258 else if (Mips::ACC64RegClass.hasSubClassEq(RC)) in storeRegToStack()
260 else if (Mips::ACC64DSPRegClass.hasSubClassEq(RC)) in storeRegToStack()
262 else if (Mips::ACC128RegClass.hasSubClassEq(RC)) in storeRegToStack()
264 else if (Mips::DSPCCRegClass.hasSubClassEq(RC)) in storeRegToStack()
266 else if (Mips::FGR32RegClass.hasSubClassEq(RC)) in storeRegToStack()
268 else if (Mips::AFGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
270 else if (Mips::FGR64RegClass.hasSubClassEq(RC)) in storeRegToStack()
283 else if (Mips::LO32RegClass.hasSubClassEq(RC)) in storeRegToStack()
[all …]
H A DMips16InstrInfo.cpp116 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in storeRegToStack()
135 if (Mips::CPU16RegsRegClass.hasSubClassEq(RC)) in loadRegFromStack()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64InstrInfo.cpp551 bool Is64Bit = AArch64::GPR64allRegClass.hasSubClassEq(MRI.getRegClass(VReg)); in canFoldIntoCSel()
635 if (AArch64::GPR64allRegClass.hasSubClassEq(RC) || in canInsertSelect()
636 AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in canInsertSelect()
649 if (AArch64::FPR64RegClass.hasSubClassEq(RC) || in canInsertSelect()
650 AArch64::FPR32RegClass.hasSubClassEq(RC)) { in canInsertSelect()
1212 } else if (!OpRegCstraints->hasSubClassEq(MRI->getRegClass(Reg)) && in UpdateOperandRegClass()
3614 if (AArch64::FPR8RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3618 if (AArch64::FPR16RegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
3620 else if (AArch64::PPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
3627 if (AArch64::GPR32allRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp1552 if (!PPC::GPRCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1553 !PPC::GPRC_NOR0RegClass.hasSubClassEq(RC) && in canInsertSelect()
1554 !PPC::G8RCRegClass.hasSubClassEq(RC) && in canInsertSelect()
1555 !PPC::G8RC_NOX0RegClass.hasSubClassEq(RC)) in canInsertSelect()
1583 bool Is64Bit = PPC::G8RCRegClass.hasSubClassEq(RC) || in insertSelect()
1584 PPC::G8RC_NOX0RegClass.hasSubClassEq(RC); in insertSelect()
1586 PPC::GPRCRegClass.hasSubClassEq(RC) || in insertSelect()
1587 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) && in insertSelect()
1851 if (PPC::GPRCRegClass.hasSubClassEq(RC) || in getSpillIndex()
1852 PPC::GPRC_NOR0RegClass.hasSubClassEq(RC)) { in getSpillIndex()
[all …]
H A DPPCVSXCopy.cpp54 return RC->hasSubClassEq(MRI.getRegClass(Reg)); in IsRegInClass()
H A DPPCVSXSwapRemoval.cpp162 return RC->hasSubClassEq(MRI->getRegClass(Reg)); in isRegInClass()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Sparc/
H A DSparcInstrInfo.cpp421 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
424 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in storeRegToStackSlot()
459 else if (SP::DFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
462 else if (SP::QFPRegsRegClass.hasSubClassEq(RC)) in loadRegFromStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/M68k/
H A DM68kInstrInfo.cpp717 if (M68k::DR8RegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
719 if (M68k::CCRCRegClass.hasSubClassEq(RC)) in getLoadStoreRegOpcode()
724 assert(M68k::XR16RegClass.hasSubClassEq(RC) && "Unknown 2-byte regclass"); in getLoadStoreRegOpcode()
727 assert(M68k::XR32RegClass.hasSubClassEq(RC) && "Unknown 4-byte regclass"); in getLoadStoreRegOpcode()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h120 return RC != this && hasSubClassEq(RC); in hasSubClass()
124 bool hasSubClassEq(const TargetRegisterClass *RC) const { in hasSubClassEq() function
137 return RC->hasSubClassEq(this); in hasSuperClassEq()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp48 if (!RC.hasSubClassEq(&SubRC)) in verify()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/
H A DARCInstrInfo.cpp311 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
338 assert(ARC::GPR32RegClass.hasSubClassEq(RC) && in loadRegFromStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DThumb2InstrInfo.cpp177 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
187 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
219 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
228 if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
H A DARMBaseInstrInfo.cpp1128 if (ARM::HPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1139 if (ARM::GPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1146 } else if (ARM::SPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1153 } else if (ARM::VCCRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1164 if (ARM::DPRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1171 } else if (ARM::GPRPairRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1192 if (ARM::DPairRegClass.hasSubClassEq(RC) && Subtarget.hasNEON()) { in storeRegToStackSlot()
1208 } else if (ARM::QPRRegClass.hasSubClassEq(RC) && in storeRegToStackSlot()
1220 if (ARM::DTripleRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
1244 if (ARM::QQPRRegClass.hasSubClassEq(RC) || ARM::DQuadRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
[all …]
H A DThumbRegisterInfo.cpp48 if (ARM::tGPRRegClass.hasSubClassEq(RC)) in getLargestLegalSuperClass()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp925 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
929 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
933 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
937 } else if (Hexagon::ModRegsRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
941 } else if (Hexagon::HvxQRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
945 } else if (Hexagon::HvxVRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
949 } else if (Hexagon::HvxWRRegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
970 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
973 } else if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
976 } else if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()
[all …]
H A DHexagonConstPropagation.cpp2368 if (Hexagon::IntRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2370 if (Hexagon::DoubleRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
2372 if (Hexagon::PredRegsRegClass.hasSubClassEq(RC)) in getRegBitWidth()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZRegisterInfo.cpp32 if (SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in getRC32()
36 if (SystemZ::GRH32BitRegClass.hasSubClassEq(RC) || in getRC32()
H A DSystemZInstrInfo.cpp554 SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) || in canInsertSelect()
555 SystemZ::GR32BitRegClass.hasSubClassEq(RC) || in canInsertSelect()
556 SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in canInsertSelect()
581 if (SystemZ::GRX32BitRegClass.hasSubClassEq(RC)) { in insertSelect()
596 } else if (SystemZ::GR64BitRegClass.hasSubClassEq(RC)) { in insertSelect()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRRegisterInfo.cpp286 if(this->getRegClass(AVR::PTRDISPREGSRegClassID)->hasSubClassEq(NewRC)) { in shouldCoalesce()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp59 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in storeRegToStackSlot()
79 if (!Lanai::GPRRegClass.hasSubClassEq(RegisterClass)) { in loadRegFromStackSlot()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/
H A DVEInstrInfo.cpp492 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in storeRegToStackSlot()
536 } else if (VE::F128RegClass.hasSubClassEq(RC)) { in loadRegFromStackSlot()

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