Searched refs:hasSVE (Results 1 – 7 of 7) sorted by relevance
114 if (ST->hasSVE()) in getRegisterBitWidth()119 return TypeSize::getScalable(ST->hasSVE() ? 128 : 0); in getRegisterBitWidth()129 if (ST->hasSVE()) in getMaxVScale()227 if (!ST->hasSVE()) in isLegalMaskedLoadStore()246 if (isa<FixedVectorType>(DataType) || !ST->hasSVE()) in isLegalMaskedGatherScatter()293 bool supportsScalableVectors() const { return ST->hasSVE(); } in supportsScalableVectors()
383 return hasSVE() && getMinSVEVectorSizeInBits() >= 256; in useSVEForFixedLengthVectors()
399 if (MF.getSubtarget<AArch64Subtarget>().hasSVE()) { in hasBasePointer()448 assert((!MF.getSubtarget<AArch64Subtarget>().hasSVE() || in useFPForScavengingIndex()
448 bool hasSVE() const { return HasSVE; } in hasSVE() function
3289 assert(Subtarget.hasSVE() && "Unexpected SVE register."); in copyPhysReg()3300 assert(Subtarget.hasSVE() && "Unexpected SVE register."); in copyPhysReg()3621 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()3665 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()3687 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()3698 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()3709 assert(Subtarget.hasSVE() && "Unexpected register store without SVE"); in storeRegToStackSlot()3775 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()3819 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()3841 assert(Subtarget.hasSVE() && "Unexpected register load without SVE"); in loadRegFromStackSlot()[all …]
281 if (Subtarget->hasSVE()) { in AArch64TargetLowering()1116 if (Subtarget->hasSVE()) in AArch64TargetLowering()1122 if (Subtarget->hasSVE()) { in AArch64TargetLowering()
113 def HasSVE : Predicate<"Subtarget->hasSVE()">,