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Searched refs:grph (Results 1 – 12 of 12) sorted by relevance

/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn20/
H A Damdgpu_dcn20_hubbub.c287 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
288 output->grph.rgb.max_compressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
289 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
292 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
293 output->grph.rgb.max_compressed_blk_size = 128; in hubbub2_get_dcc_compression_cap()
294 output->grph.rgb.independent_64b_blks = false; in hubbub2_get_dcc_compression_cap()
297 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub2_get_dcc_compression_cap()
298 output->grph.rgb.max_compressed_blk_size = 64; in hubbub2_get_dcc_compression_cap()
299 output->grph.rgb.independent_64b_blks = true; in hubbub2_get_dcc_compression_cap()
H A Damdgpu_dcn20_hubp.c723 if (address->grph.addr.quad_part == 0) in hubp2_program_surface_flip_and_addr()
730 if (address->grph.meta_addr.quad_part != 0) { in hubp2_program_surface_flip_and_addr()
733 address->grph.meta_addr.high_part); in hubp2_program_surface_flip_and_addr()
737 address->grph.meta_addr.low_part); in hubp2_program_surface_flip_and_addr()
742 address->grph.addr.high_part); in hubp2_program_surface_flip_and_addr()
746 address->grph.addr.low_part); in hubp2_program_surface_flip_and_addr()
900 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp2_is_flip_pending()
903 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp2_is_flip_pending()
908 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp2_is_flip_pending()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn10/
H A Damdgpu_dcn10_hubbub.c924 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
925 output->grph.rgb.max_compressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
926 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
929 output->grph.rgb.max_uncompressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
930 output->grph.rgb.max_compressed_blk_size = 128; in hubbub1_get_dcc_compression_cap()
931 output->grph.rgb.independent_64b_blks = false; in hubbub1_get_dcc_compression_cap()
934 output->grph.rgb.max_uncompressed_blk_size = 256; in hubbub1_get_dcc_compression_cap()
935 output->grph.rgb.max_compressed_blk_size = 64; in hubbub1_get_dcc_compression_cap()
936 output->grph.rgb.independent_64b_blks = true; in hubbub1_get_dcc_compression_cap()
H A Damdgpu_dcn10_hubp.c381 if (address->grph.addr.quad_part == 0) in hubp1_program_surface_flip_and_addr()
388 if (address->grph.meta_addr.quad_part != 0) { in hubp1_program_surface_flip_and_addr()
391 address->grph.meta_addr.high_part); in hubp1_program_surface_flip_and_addr()
395 address->grph.meta_addr.low_part); in hubp1_program_surface_flip_and_addr()
400 address->grph.addr.high_part); in hubp1_program_surface_flip_and_addr()
404 address->grph.addr.low_part); in hubp1_program_surface_flip_and_addr()
734 SURFACE_EARLIEST_INUSE_ADDRESS, &earliest_inuse_address.grph.addr.low_part); in hubp1_is_flip_pending()
737 SURFACE_EARLIEST_INUSE_ADDRESS_HIGH, &earliest_inuse_address.grph.addr.high_part); in hubp1_is_flip_pending()
742 if (earliest_inuse_address.grph.addr.quad_part != hubp->request_address.grph.addr.quad_part) in hubp1_is_flip_pending()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/core/
H A Damdgpu_dc_debug.c88 plane_state->address.grph.addr.quad_part, in pre_surface_trace()
89 plane_state->address.grph.meta_addr.quad_part, in pre_surface_trace()
200 update->flip_addr->address.grph.addr.quad_part, in update_surface_trace()
201 update->flip_addr->address.grph.meta_addr.quad_part, in update_surface_trace()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dcn21/
H A Damdgpu_dcn21_hubp.c810 if (address->grph.addr.quad_part == 0) { in hubp21_program_surface_flip_and_addr()
815 if (address->grph.meta_addr.quad_part != 0) { in hubp21_program_surface_flip_and_addr()
817 address->grph.meta_addr.low_part; in hubp21_program_surface_flip_and_addr()
819 address->grph.meta_addr.high_part; in hubp21_program_surface_flip_and_addr()
823 address->grph.addr.low_part; in hubp21_program_surface_flip_and_addr()
825 address->grph.addr.high_part; in hubp21_program_surface_flip_and_addr()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce/
H A Damdgpu_dce_mem_input.c710 if (address->grph.addr.quad_part == 0) in dce_mi_program_surface_flip_and_addr()
712 program_pri_addr(dce_mi, address->grph.addr); in dce_mi_program_surface_flip_and_addr()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/
H A Ddc_hw_types.h77 } grph; member
H A Ddc.h150 } grph; member
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/dc/dce110/
H A Damdgpu_dce110_mem_input_v.c143 addr->grph.addr); in program_addr()
H A Damdgpu_dce110_hw_sequencer.c2538 pipe_ctx->plane_state->address.grph.addr.high_part, in dce110_program_front_end_for_pipe()
2539 pipe_ctx->plane_state->address.grph.addr.low_part, in dce110_program_front_end_for_pipe()
/netbsd-src/sys/external/bsd/drm2/dist/drm/amd/display/amdgpu_dm/
H A Damdgpu_dm.c3186 if (i64b == 0 && output.grph.rgb.independent_64b_blks != 0) in fill_plane_dcc_attributes()
3195 address->grph.meta_addr.low_part = lower_32_bits(dcc_address); in fill_plane_dcc_attributes()
3196 address->grph.meta_addr.high_part = upper_32_bits(dcc_address); in fill_plane_dcc_attributes()
3229 address->grph.addr.low_part = lower_32_bits(afb->address); in fill_plane_buffer_attributes()
3230 address->grph.addr.high_part = upper_32_bits(afb->address); in fill_plane_buffer_attributes()
6489 bundle->flip_addrs[planes_count].address.grph.addr.high_part, in amdgpu_dm_commit_planes()
6490 bundle->flip_addrs[planes_count].address.grph.addr.low_part); in amdgpu_dm_commit_planes()