Searched refs:getWavefrontSize (Results 1 – 20 of 20) sorted by relevance
180 unsigned getWavefrontSize() const { in getWavefrontSize() function
1091 return getWavefrontSize() == 32; in isWave32()1095 return getWavefrontSize() == 64; in isWave64()
375 const unsigned WaveSize = getWavefrontSize(); in getOccupancyWithLocalMemSize()419 return std::make_pair(1, getWavefrontSize()); in getDefaultFlatWorkGroupSize()617 return getWavefrontSize() == 32 ? AMDGPUDwarfFlavour::Wave32 in getAMDGPUDwarfFlavour()
267 unsigned WaveSize = ST.getWavefrontSize(); in haveFreeLanesForSGPRSpill()284 unsigned WaveSize = ST.getWavefrontSize(); in allocateSGPRSpillToVGPR()
495 Type *const WaveTy = B.getIntNTy(ST->getWavefrontSize()); in optimizeAtomic()547 Value *const LastLaneIdx = B.getInt32(ST->getWavefrontSize() - 1); in optimizeAtomic()
81 if (ST->getWavefrontSize() == 64) { in requiresWorkAroundForInst()92 assert(ST->getWavefrontSize() == 32); in requiresWorkAroundForInst()
208 HSACodeProps.mWavefrontSize = STM.getWavefrontSize(); in getHSACodeProps()868 Kern.getDocument()->getNode(STM.getWavefrontSize()); in getHSAKernelProps()
1086 GCNSubtarget::MaxWaveScratchSize / STM.getWavefrontSize(); in getSIProgramInfo()1226 alignTo(ProgInfo.ScratchSize * STM.getWavefrontSize(), in getSIProgramInfo()
99 ST->getWavefrontSize(); in isLaneMaskReg()
679 const unsigned WavefrontSize = ST.getWavefrontSize(); in lowerInitExec()
386 return ST.enableFlatScratch() ? 1 : ST.getWavefrontSize(); in getScratchScaleFactor()
1075 if (MRI->getType(Dst).getSizeInBits() != STI.getWavefrontSize()) in selectIntrinsicIcmp()1105 if (Size != STI.getWavefrontSize()) in selectBallot()1440 if (WGSize <= STI.getWavefrontSize()) { in selectSBarrier()
1379 unsigned N = ST.getWavefrontSize(); in fold_wavefrontsize()
9 def isWave32 : Predicate<"Subtarget->getWavefrontSize() == 32">,11 def isWave64 : Predicate<"Subtarget->getWavefrontSize() == 64">,
4701 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerICMPIntrinsic()4732 unsigned WavefrontSize = TLI.getSubtarget()->getWavefrontSize(); in lowerFCMPIntrinsic()6547 return DAG.getConstant(MF.getSubtarget<GCNSubtarget>().getWavefrontSize(), in LowerINTRINSIC_WO_CHAIN()7570 if (WGSize <= ST.getWavefrontSize()) in LowerINTRINSIC_VOID()12184 return Subtarget->getWavefrontSize() == 64 ? &AMDGPU::SReg_64RegClass in getRegClassFor()12277 return hasCFUser(V, Visited, Subtarget->getWavefrontSize()); in requiresUniformRegister()
1079 Offset *= ST.getWavefrontSize(); in buildSpillLoadStore()
6140 const TargetRegisterClass *TC = ST.getWavefrontSize() == 64 in lowerSelect()6149 unsigned Opcode = (ST.getWavefrontSize() == 64) ? AMDGPU::S_CSELECT_B64 in lowerSelect()7003 uint64_t IndexStride = ST.getWavefrontSize() == 64 ? 3 : 2; in getScratchRsrcWords23()
4819 B.buildConstant(MI.getOperand(0), ST.getWavefrontSize()); in legalizeIntrinsic()
161 unsigned getWavefrontSize(const MCSubtargetInfo *STI);
517 unsigned getWavefrontSize(const MCSubtargetInfo *STI) { in getWavefrontSize() function588 return divideCeil(FlatWorkGroupSize, getWavefrontSize(STI)); in getWavesPerWorkGroup()