Home
last modified time | relevance | path

Searched refs:getUniqueVRegDef (Results 1 – 25 of 37) sorted by relevance

12

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/
H A DNVPTXPeephole.cpp85 GenericAddrDef = MRI.getUniqueVRegDef(Op.getReg()); in isCVTAToLocalCombinationCandidate()
109 auto &Prev = *MRI.getUniqueVRegDef(Root.getOperand(1).getReg()); in CombineCVTAToLocal()
148 if (auto MI = MRI.getUniqueVRegDef(NVPTX::VRFrame)) { in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/BPF/
H A DBPFMISimplifyPatchable.cpp105 if (!MRI->getUniqueVRegDef(I->getReg())) in checkADDrr()
174 if (!MRI->getUniqueVRegDef(I->getReg())) in processCandidate()
205 if (IsAma && MRI->getUniqueVRegDef(I->getReg())) in processDstReg()
273 MachineInstr *DefInst = MRI->getUniqueVRegDef(SrcReg); in removeLD()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86WinAllocaExpander.cpp86 MachineInstr *Def = MRI->getUniqueVRegDef(AmountReg); in getWinAllocaAmount()
270 if (MachineInstr *AmountDef = MRI->getUniqueVRegDef(AmountReg)) in lower()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DTargetInstrInfo.cpp711 MI1 = MRI.getUniqueVRegDef(Op1.getReg()); in hasReassociableOperands()
713 MI2 = MRI.getUniqueVRegDef(Op2.getReg()); in hasReassociableOperands()
723 MachineInstr *MI1 = MRI.getUniqueVRegDef(Inst.getOperand(1).getReg()); in hasReassociableSibling()
724 MachineInstr *MI2 = MRI.getUniqueVRegDef(Inst.getOperand(2).getReg()); in hasReassociableSibling()
903 Prev = MRI.getUniqueVRegDef(Root.getOperand(1).getReg()); in genAlternativeCodeSequence()
907 Prev = MRI.getUniqueVRegDef(Root.getOperand(2).getReg()); in genAlternativeCodeSequence()
H A DModuloSchedule.cpp1356 MachineInstr *Producer = MRI.getUniqueVRegDef(Reg); in remapUse()
1386 LoopProducer = MRI.getUniqueVRegDef(LoopReg); in remapUse()
1697 MachineInstr *Use = MRI.getUniqueVRegDef(MO.getReg()); in moveStageBetweenBlocks()
1799 MachineInstr *Use = MRI.getUniqueVRegDef(Reg); in peelPrologAndEpilogs()
1888 MachineInstr *MI = MRI.getUniqueVRegDef(Reg); in getEquivalentRegisterIn()
1899 int RMIStage = getStage(MRI.getUniqueVRegDef(R)); in rewriteUsesOf()
H A DEarlyIfConversion.cpp570 const MachineInstr *TDef = MRI.getUniqueVRegDef(TReg); in hasSameValue()
571 const MachineInstr *FDef = MRI.getUniqueVRegDef(FReg); in hasSameValue()
H A DMachineCombiner.cpp155 DefInstr = MRI->getUniqueVRegDef(MO.getReg()); in getOperandDef()
H A DMachineRegisterInfo.cpp411 MachineInstr *MachineRegisterInfo::getUniqueVRegDef(Register Reg) const { in getUniqueVRegDef() function in MachineRegisterInfo
H A DTargetRegisterInfo.cpp72 MachineInstr *MI = MRI.getUniqueVRegDef(VirtReg.reg()); in shouldRegionSplitForVirtReg()
H A DRegAllocFast.cpp352 SelfLoopDef = MRI->getUniqueVRegDef(VirtReg); in mayLiveOut()
700 MachineInstr *VRegDef = MRI->getUniqueVRegDef(Reg); in traceCopyChain()
H A DMachineCSE.cpp664 MachineInstr *Def = MRI->getUniqueVRegDef(NewReg); in ProcessBlockCSE()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSILowerControlFlow.cpp366 if (MachineInstr *Def = MRI->getUniqueVRegDef(MI.getOperand(1).getReg())) { in emitIfBreak()
505 MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg()); in findMaskOperands()
547 MRI->getUniqueVRegDef(Reg)->eraseFromParent(); in combineMasks()
568 const MachineInstr *Def = MRI->getUniqueVRegDef(SavedExec); in optimizeEndCf()
H A DSILowerI1Copies.cpp573 MachineInstr *IncomingDef = MRI->getUniqueVRegDef(IncomingReg); in lowerPhis()
734 MI = MRI->getUniqueVRegDef(Reg); in isConstantLaneMask()
H A DGCNNSAReassign.cpp201 const MachineInstr *Def = MRI->getUniqueVRegDef(Reg); in CheckNSA()
H A DR600OptimizeVectorRegisters.cpp43 const MachineInstr *MI = MRI.getUniqueVRegDef(Reg); in isImplicitlyDef()
H A DSILoadStoreOptimizer.cpp1750 MachineInstr *Def = MRI->getUniqueVRegDef(Op.getReg()); in extractConstOffset()
1773 MachineInstr *Def = MRI->getUniqueVRegDef(Base.getReg()); in processBaseWithConstOffset()
1783 MachineInstr *BaseLoDef = MRI->getUniqueVRegDef(BaseLo.getReg()); in processBaseWithConstOffset()
1784 MachineInstr *BaseHiDef = MRI->getUniqueVRegDef(BaseHi.getReg()); in processBaseWithConstOffset()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/
H A DWebAssemblyRegisterInfo.cpp96 MachineInstr *Def = MF.getRegInfo().getUniqueVRegDef(OtherMOReg); in eliminateFrameIndex()
H A DWebAssemblyMachineFunctionInfo.h125 assert(MRI.getUniqueVRegDef(VReg)); in stackifyVReg()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64CondBrTuning.cpp83 return MRI->getUniqueVRegDef(MO.getReg()); in getOperandDef()
H A DAArch64InstrInfo.cpp1308 auto *Mask = MRI->getUniqueVRegDef(MaskReg); in optimizePTestInstr()
1309 auto *Pred = MRI->getUniqueVRegDef(PredReg); in optimizePTestInstr()
1338 auto PTestLikeMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg()); in optimizePTestInstr()
1353 auto *PredMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg()); in optimizePTestInstr()
1364 auto *PredMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg()); in optimizePTestInstr()
1376 auto *PredMask = MRI->getUniqueVRegDef(Pred->getOperand(1).getReg()); in optimizePTestInstr()
1724 MachineInstr *MI = MRI.getUniqueVRegDef(SrcReg); in substituteCmpToZero()
1848 MachineInstr *MI = MRI.getUniqueVRegDef(SrcReg); in removeCmpToZeroOrOne()
4510 MI = MRI.getUniqueVRegDef(MO.getReg()); in canCombine()
5013 MachineInstr *MUL = MRI.getUniqueVRegDef(Root.getOperand(IdxMulOpd).getReg()); in genFusedMultiply()
[all …]
H A DAArch64SIMDInstrOpt.cpp522 DefiningMI = MRI->getUniqueVRegDef(SeqReg); in optimizeLdStInterleave()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DCombinerHelper.cpp763 MachineInstr *BaseDef = MRI.getUniqueVRegDef(Base); in findPostIndexCandidate()
784 MachineInstr *OffsetDef = MRI.getUniqueVRegDef(Offset); in findPostIndexCandidate()
912 MachineInstr &AddrDef = *MRI.getUniqueVRegDef(MatchInfo.Addr); in applyCombineIndexedLoadStore()
1673 MachineInstr *Add2Def = MRI.getUniqueVRegDef(Add2); in matchPtrAddImmedChain()
1723 MachineInstr *Shl2Def = MRI.getUniqueVRegDef(Shl2); in matchShiftImmedChain()
1806 MachineInstr *LogicMI = MRI.getUniqueVRegDef(LogicDest); in matchShiftOfShiftedLogic()
1838 MachineInstr *LogicMIOp1 = MRI.getUniqueVRegDef(LogicMIReg1); in matchShiftOfShiftedLogic()
1840 MachineInstr *LogicMIOp2 = MRI.getUniqueVRegDef(LogicMIReg2); in matchShiftOfShiftedLogic()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCInstrInfo.cpp429 MachineInstr *MIAdd = MRI->getUniqueVRegDef(OpAdd.getReg()); in getFMAPatterns()
518 MachineInstr *Prev = MRI->getUniqueVRegDef(RegB); in getFMAPatterns()
528 MachineInstr *Leaf = MRI->getUniqueVRegDef(RegA); in getFMAPatterns()
825 Prev = MRI.getUniqueVRegDef(Root.getOperand(AddOpIdx).getReg()); in reassociateFMA()
826 Leaf = MRI.getUniqueVRegDef(Prev->getOperand(AddOpIdx).getReg()); in reassociateFMA()
2391 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); in optimizeCompareInstr()
5425 MachineInstr *LoopCount = MRI.getUniqueVRegDef(LoopCountReg); in analyzeLoopForPipelining()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiInstrInfo.cpp287 MachineInstr *MI = MRI->getUniqueVRegDef(SrcReg); in optimizeCompareInstr()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DMachineRegisterInfo.h608 MachineInstr *getUniqueVRegDef(Register Reg) const;

12