| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/NVPTX/ |
| H A D | NVPTXISelDAGToDAG.cpp | 885 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoad() 1023 MVT SimpleVT = LoadedVT.getSimpleVT(); in tryLoadVector() 1076 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector() 1084 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_avar, in tryLoadVector() 1103 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector() 1111 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_asi, in tryLoadVector() 1132 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v2_ari_64, in tryLoadVector() 1140 EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari_64, in tryLoadVector() 1151 Opcode = pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, in tryLoadVector() 1159 pickOpcodeForVT(EltVT.getSimpleVT().SimpleTy, NVPTX::LDV_i8_v4_ari, in tryLoadVector() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | ValueTypes.h | 96 return getSimpleVT().changeVectorElementTypeToInteger(); in changeVectorElementTypeToInteger() 106 return getSimpleVT().changeVectorElementType(EltVT.getSimpleVT()); in changeVectorElementType() 119 return getSimpleVT().changeTypeToInteger(); in changeTypeToInteger() 281 MVT getSimpleVT() const { in getSimpleVT() function
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| H A D | TargetLowering.h | 549 MVT LoadMVT = LoadVT.getSimpleVT(); in isLoadBitCastBeneficial() 554 getTypeToPromoteTo(ISD::LOAD, LoadMVT) == BitcastVT.getSimpleVT()) in isLoadBitCastBeneficial() 891 (unsigned)VT.getSimpleVT().SimpleTy < array_lengthof(RegClassForVT)); in isTypeLegal() 892 return VT.isSimple() && RegClassForVT[VT.getSimpleVT().SimpleTy] != nullptr; in isTypeLegal() 1046 return OpActions[(unsigned)VT.getSimpleVT().SimpleTy][Op]; in getOperationAction() 1223 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getLoadExtAction() 1224 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getLoadExtAction() 1248 unsigned ValI = (unsigned) ValVT.getSimpleVT().SimpleTy; in getTruncStoreAction() 1249 unsigned MemI = (unsigned) MemVT.getSimpleVT().SimpleTy; in getTruncStoreAction() 1279 (getIndexedLoadAction(IdxMode, VT.getSimpleVT()) == Legal || in isIndexedLoadLegal() [all …]
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| H A D | TargetCallingConv.h | 215 VT = vt.getSimpleVT(); in InputArg() 254 VT = vt.getSimpleVT(); in OutputArg()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | FastISel.cpp | 250 MVT VT = RealVT.getSimpleVT(); in getRegForValue() 254 VT = TLI.getTypeToTransformTo(V->getContext(), VT).getSimpleVT(); in getRegForValue() 313 Reg = fastEmit_r(IntVT.getSimpleVT(), VT, ISD::SINT_TO_FP, in materializeConstant() 396 IdxN = fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::SIGN_EXTEND, IdxN); in getRegForGEPIndex() 399 fastEmit_r(IdxVT.getSimpleVT(), PtrVT, ISD::TRUNCATE, IdxN); in getRegForGEPIndex() 481 fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op1, CI->getZExtValue(), in selectBinaryOp() 482 VT.getSimpleVT()); in selectBinaryOp() 513 Register ResultReg = fastEmit_ri_(VT.getSimpleVT(), ISDOpcode, Op0, Imm, in selectBinaryOp() 514 VT.getSimpleVT()); in selectBinaryOp() 528 Register ResultReg = fastEmit_rr(VT.getSimpleVT(), VT.getSimpleVT(), in selectBinaryOp() [all …]
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| H A D | LegalizeDAG.cpp | 312 SVT = (MVT::SimpleValueType)(SVT.getSimpleVT().SimpleTy - 1); in ExpandConstantFP() 849 SrcVT.getSimpleVT())) { in LegalizeLoadOps() 880 EVT LoadVT = TLI.getRegisterType(SrcVT.getSimpleVT()); in LegalizeLoadOps() 904 EVT ILoadVT = TLI.getRegisterType(IDestVT.getSimpleVT()); in LegalizeLoadOps() 2101 switch (InVT.getSimpleVT().SimpleTy) { in ExpandArgFPLibCall() 2463 switch (SrcVT.getSimpleVT().SimpleTy) { in ExpandLegalINT_TO_FP() 2529 NewInTy = (MVT::SimpleValueType)(NewInTy.getSimpleVT().SimpleTy+1); in PromoteLegalINT_TO_FP() 2587 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy+1); in PromoteLegalFP_TO_INT() 2630 NewOutTy = (MVT::SimpleValueType)(NewOutTy.getSimpleVT().SimpleTy + 1); in PromoteLegalFP_TO_INT_SAT() 3897 MVT VT = cast<AtomicSDNode>(Node)->getMemoryVT().getSimpleVT(); in ConvertNodeToLibcall()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMTargetTransformInfo.cpp | 455 LoadConversionTbl, ISD, DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost() 478 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost() 490 DstTy.getSimpleVT(), SrcTy.getSimpleVT())) in getCastInstrCost() 507 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost() 518 SrcTy.getSimpleVT(), DstTy.getSimpleVT())) in getCastInstrCost() 544 DstTy.getSimpleVT(), in getCastInstrCost() 545 SrcTy.getSimpleVT())) { in getCastInstrCost() 655 DstTy.getSimpleVT(), in getCastInstrCost() 656 SrcTy.getSimpleVT())) in getCastInstrCost() 685 DstTy.getSimpleVT(), in getCastInstrCost() [all …]
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| H A D | ARMFastISel.cpp | 631 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() 678 VT = evt.getSimpleVT(); in isTypeLegal() 1339 MVT SrcVT = SrcEVT.getSimpleVT(); in ARMEmitCmp() 1534 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() 1776 MVT VT = FPVT.getSimpleVT(); in SelectBinaryFPOp() 2123 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet() 2187 return ARMMaterializeGV(GV, LCREVT.getSimpleVT()); in getLibcallReg() 2754 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt() 2755 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt() 3039 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments()
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| H A D | ARMCallLowering.cpp | 75 unsigned VTSize = VT.getSimpleVT().getSizeInBits(); in isSupportedType()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/MSP430/ |
| H A D | MSP430ISelDAGToDAG.cpp | 305 switch (VT.getSimpleVT().SimpleTy) { in isValidIndexedLoad() 330 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedLoad() 359 MVT VT = LD->getMemoryVT().getSimpleVT(); in tryIndexedBinOp()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/ |
| H A D | AVRISelDAGToDAG.cpp | 107 MVT VT = cast<MemSDNode>(Op)->getMemoryVT().getSimpleVT(); in SelectAddr() 124 MVT VT = LD->getMemoryVT().getSimpleVT(); in selectIndexedLoad() 368 MVT VT = LD->getMemoryVT().getSimpleVT(); in select()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/ |
| H A D | MipsFastISel.cpp | 452 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() 600 VT = evt.getSimpleVT(); in isTypeLegal() 1371 switch (ArgVT.getSimpleVT().SimpleTy) { in fastLowerArguments() 1740 MVT RVVT = RVEVT.getSimpleVT(); in selectRet() 1819 MVT SrcVT = SrcEVT.getSimpleVT(); in selectIntExt() 1820 MVT DestVT = DestEVT.getSimpleVT(); in selectIntExt() 1920 MVT DestVT = DestEVT.getSimpleVT(); in selectDivRem() 1981 MVT Op0MVT = TLI.getValueType(DL, Op0->getType(), true).getSimpleVT(); in selectShift() 2097 MVT VMVT = TLI.getValueType(DL, V->getType(), true).getSimpleVT(); in getRegEnsuringSimpleIntegerWidening()
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| H A D | MipsSEISelDAGToDAG.cpp | 1264 TLI->getRegClassFor(ViaVecTy.getSimpleVT()); in trySelect() 1332 MVT ResVecTySimple = ResVecTy.getSimpleVT(); in trySelect()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonISelDAGToDAG.cpp | 81 switch (LoadedVT.getSimpleVT().SimpleTy) { in SelectIndexedLoad() 477 switch (StoredVT.getSimpleVT().SimpleTy) { in SelectIndexedStore() 771 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectVAlign() 834 MVT OpTy = Op.getValueType().getSimpleVT(); in SelectTypecast() 841 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectP2D() 849 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectD2P() 858 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectV2Q() 860 MVT OpTy = N->getOperand(0).getValueType().getSimpleVT(); (void)OpTy; in SelectV2Q() 872 MVT ResTy = N->getValueType(0).getSimpleVT(); in SelectQ2V() 1170 if (!OpVT.isSimple() || OpVT.getSimpleVT() != MVT::i1) in ppHoistZextI1() [all …]
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| H A D | HexagonISelLowering.h | 386 return Op.getValueType().getSimpleVT(); in ty() 389 return { Ops.first.getValueType().getSimpleVT(), in ty() 390 Ops.second.getValueType().getSimpleVT() }; in ty()
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| H A D | HexagonISelDAGToDAGHVX.cpp | 673 : InpNode(Inp), InpTy(Inp->getValueType(0).getSimpleVT()) {} in ResultStack() 989 MVT OpTy = Op.getValueType().getSimpleVT(); in materialize() 1442 MVT LegalTy = Lower.getTypeToTransformTo(Ctx, ElemTy).getSimpleVT(); in scalarizeShuffle() 2046 MVT ResTy = N->getValueType(0).getSimpleVT(); in selectShuffle() 2118 MVT Ty = N->getValueType(0).getSimpleVT(); in selectRor()
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| H A D | HexagonISelLoweringHVX.cpp | 359 MVT CastTy = tyVector(Vec.getValueType().getSimpleVT(), ElemTy); in opCastElem() 425 if (ElemIdx.getValueType().getSimpleVT() != MVT::i32) in convertToByteIndex() 1776 MVT Ty = typeSplit(N->getVT().getSimpleVT()).first; in SplitHvxPairOp() 1806 MVT MemTy = MemN->getMemoryVT().getSimpleVT(); in SplitHvxMemOp() 2293 return Subtarget.isHVXVectorType(WideTy.getSimpleVT(), true); in shouldWidenToHvx() 2305 return Ty.isSimple() && Subtarget.isHVXVectorType(Ty.getSimpleVT(), true); in isHvxOperation()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/ |
| H A D | X86FastISel.cpp | 302 VT = evt.getSimpleVT(); in isTypeLegal() 499 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore() 671 switch (VT.getSimpleVT().SimpleTy) { in X86FastEmitStore() 710 unsigned RR = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Opc, Src); in X86FastEmitExtend() 1266 SrcReg = fastEmit_r(SrcVT.getSimpleVT(), DstVT.getSimpleVT(), Op, SrcReg); in X86SelectRet() 1364 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpOpcode() 1387 switch (VT.getSimpleVT().SimpleTy) { in X86ChooseCmpImmediateOpcode() 1590 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::ZERO_EXTEND, in X86SelectZExt() 1634 ResultReg = fastEmit_r(MVT::i8, DstVT.getSimpleVT(), ISD::SIGN_EXTEND, in X86SelectSExt() 2440 MVT DstVT = TLI.getValueType(DL, I->getType()).getSimpleVT(); in X86SelectIntToFP() [all …]
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCFastISel.cpp | 275 VT = Evt.getSimpleVT(); in isTypeLegal() 825 MVT SrcVT = SrcEVT.getSimpleVT(); in PPCEmitCmp() 1075 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIToFP() 1752 MVT RVVT = RVEVT.getSimpleVT(); in SelectRet() 1916 MVT SrcVT = SrcEVT.getSimpleVT(); in SelectIntExt() 1917 MVT DestVT = DestEVT.getSimpleVT(); in SelectIntExt() 2255 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetLoweringBase.cpp | 933 MVT SVT = VT.getSimpleVT(); in getTypeConversion() 1022 MVT NVT = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion() 1045 MVT LargerVector = MVT::getVectorVT(EltVT.getSimpleVT(), NumElts); in getTypeConversion() 1520 RegisterVT = RegisterEVT.getSimpleVT(); in getVectorTypeBreakdown() 1827 return std::make_pair(Cost, MTy.getSimpleVT()); in getTypeLegalizationCost() 1834 return std::make_pair(Cost, MTy.getSimpleVT()); in getTypeLegalizationCost()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/ |
| H A D | WebAssemblyFastISel.cpp | 120 return VT.isSimple() ? VT.getSimpleVT().SimpleTy in getSimpleType() 1169 Register Reg = fastEmit_ISD_BITCAST_r(VT.getSimpleVT(), RetVT.getSimpleVT(), in selectBitCast()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/ |
| H A D | AArch64TargetTransformInfo.cpp | 845 DstTy.getSimpleVT(), in getCastInstrCost() 846 SrcTy.getSimpleVT())) in getCastInstrCost() 1147 SelCondTy.getSimpleVT(), in getCmpSelInstrCost() 1148 SelValTy.getSimpleVT())) in getCmpSelInstrCost()
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| H A D | AArch64FastISel.cpp | 516 MVT VT = CEVT.getSimpleVT(); in fastMaterializeConstant() 967 VT = evt.getSimpleVT(); in isTypeLegal() 1453 MVT VT = EVT.getSimpleVT(); in emitCmp() 2856 emitIntExt(SrcVT.getSimpleVT(), SrcReg, MVT::i32, /*isZExt*/ !Signed); in selectIntToFP() 2915 MVT VT = ArgVT.getSimpleVT().SimpleTy; in fastLowerArguments() 3816 MVT RVVT = RVEVT.getSimpleVT(); in selectRet() 3867 MVT SrcVT = SrcEVT.getSimpleVT(); in selectTrunc() 3868 MVT DestVT = DestEVT.getSimpleVT(); in selectTrunc() 4524 MVT DestVT = DestEVT.getSimpleVT(); in selectRem() 4873 IdxN = emitIntExt(IdxVT.getSimpleVT(), IdxN, PtrVT, /*isZExt=*/false); in getRegForGEPIndex()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARC/ |
| H A D | ARCISelLowering.cpp | 485 switch (RegVT.getSimpleVT().SimpleTy) { in LowerCallArguments() 488 << (unsigned)RegVT.getSimpleVT().SimpleTy << "\n"); in LowerCallArguments()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/ |
| H A D | InlineAsmLowering.cpp | 328 OpInfo.ConstraintVT = TLI->getValueType(DL, OpTy, true).getSimpleVT(); in lowerInlineAsm()
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