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Searched refs:getSUnit (Results 1 – 25 of 28) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DScheduleDAG.cpp112 if (!Required && PredDep.getSUnit() == D.getSUnit()) in addPred()
118 SUnit *PredSU = PredDep.getSUnit(); in addPred()
136 SUnit *N = D.getSUnit(); in addPred()
183 SUnit *N = D.getSUnit(); in removePred()
225 SUnit *SuccSU = SuccDep.getSUnit(); in setDepthDirty()
240 SUnit *PredSU = PredDep.getSUnit(); in setHeightDirty()
273 SUnit *PredSU = PredDep.getSUnit(); in ComputeDepth()
304 SUnit *SuccSU = SuccDep.getSUnit(); in ComputeHeight()
330 unsigned MaxDepth = BestI->getSUnit()->getDepth(); in biasCriticalPath()
333 if (I->getKind() == SDep::Data && I->getSUnit()->getDepth() > MaxDepth) in biasCriticalPath()
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H A DMachinePipeliner.cpp626 NewInstrChanges[KV.first] = InstrChanges[getSUnit(KV.first)]; in schedule()
693 SUnit *SuccSU = SI.getSUnit(); in isSuccOrder()
861 SUnit *SU = getSUnit(UseMI); in updatePhiDependences()
881 SUnit *SU = getSUnit(DefMI); in updatePhiDependences()
902 MachineInstr *PMI = PI.getSUnit()->getInstr(); in updatePhiDependences()
936 SUnit *DefSU = getSUnit(DefMI); in changeDependences()
943 SUnit *LastSU = getSUnit(LastMI); in changeDependences()
953 if (P.getSUnit() == DefSU) in changeDependences()
956 Topo.RemovePred(&I, Deps[i].getSUnit()); in changeDependences()
962 if (P.getSUnit() == &I && P.getKind() == SDep::Order) in changeDependences()
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H A DMacroFusion.cpp42 return SI.getSUnit(); in getPredClusterSU()
84 if (SI.getSUnit() == &SecondSU) in fuseInstructionPair()
88 if (SI.getSUnit() == &FirstSU) in fuseInstructionPair()
101 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
114 SUnit *SU = SI.getSUnit(); in fuseInstructionPair()
183 SUnit &DepSU = *Dep.getSUnit(); in scheduleAdjacentImpl()
H A DLatencyPriorityQueue.cpp59 SUnit &Pred = *P.getSUnit(); in getSingleUnscheduledPred()
78 if (getSingleUnscheduledPred(I->getSUnit()) == SU) in push()
93 AdjustPriorityOfUnscheduledPreds(Succ.getSUnit()); in scheduledNode()
H A DScheduleDAGInstrs.cpp1211 if (Topo.IsReachable(PredDep.getSUnit(), SuccSU)) in addEdge()
1213 Topo.AddPredQueued(SuccSU, PredDep.getSUnit()); in addEdge()
1289 unsigned PredNum = PredDep.getSUnit()->NodeNum; in visitPostorderNode()
1317 += R.DFSNodeData[PredDep.getSUnit()->NodeNum].InstrCount; in visitPostorderEdge()
1323 ConnectionPairs.push_back(std::make_pair(PredDep.getSUnit(), Succ)); in visitCrossEdge()
1370 const SUnit *PredSU = PredDep.getSUnit(); in joinPredSubtree()
1446 !SuccDep.getSUnit()->isBoundaryNode()) in hasDataSucc()
1473 || PredDep.getSUnit()->isBoundaryNode()) { in compute()
1477 if (Impl.isVisited(PredDep.getSUnit())) { in compute()
1481 Impl.visitPreorder(PredDep.getSUnit()); in compute()
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H A DMachineScheduler.cpp638 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
675 SUnit *PredSU = PredEdge->getSUnit(); in releasePred()
931 if (SUnit *SU = getSUnit(&MI)) in dumpSchedule()
1352 const SUnit *DefSU = getSUnit(DefMI); in computeCyclicCriticalPath()
1650 if (Succ.getSUnit() == SUb) in clusterNeighboringMemOps()
1652 LLVM_DEBUG(dbgs() << " Copy Succ SU(" << Succ.getSUnit()->NodeNum in clusterNeighboringMemOps()
1654 DAG->addEdge(Succ.getSUnit(), SDep(SUb, SDep::Artificial)); in clusterNeighboringMemOps()
1664 if (Pred.getSUnit() == SUa) in clusterNeighboringMemOps()
1666 LLVM_DEBUG(dbgs() << " Copy Pred SU(" << Pred.getSUnit()->NodeNum in clusterNeighboringMemOps()
1668 DAG->addEdge(SUa, SDep(Pred.getSUnit(), SDep::Artificial)); in clusterNeighboringMemOps()
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H A DAggressiveAntiDepBreaker.cpp277 const SUnit *PredSU = Pred.getSUnit(); in CriticalPathStep()
290 return (Next) ? Next->getSUnit() : nullptr; in CriticalPathStep()
844 SUnit *NextSU = Edge->getSUnit(); in BreakAntiDependencies()
887 if (Pred.getSUnit() == NextSU ? (Pred.getKind() != SDep::Anti || in BreakAntiDependencies()
896 if ((Pred.getSUnit() == NextSU) && (Pred.getKind() != SDep::Anti) && in BreakAntiDependencies()
901 } else if ((Pred.getSUnit() != NextSU) && in BreakAntiDependencies()
H A DCriticalAntiDepBreaker.cpp146 const SUnit *PredSU = P.getSUnit(); in CriticalPathStep()
560 const SUnit *NextSU = Edge->getSUnit(); in BreakAntiDependencies()
583 if (P.getSUnit() == NextSU in BreakAntiDependencies()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DGCNMinRegStrategy.cpp90 for (auto PDep : SDep.getSUnit()->Preds) { in getReadySuccessors()
91 auto PSU = PDep.getSUnit(); in getReadySuccessors()
180 if (S.getSUnit()->isBoundaryNode() || isScheduled(S.getSUnit()) || in bumpPredsPriority()
183 for (const auto &P : S.getSUnit()->Preds) { in bumpPredsPriority()
184 auto PSU = P.getSUnit(); in bumpPredsPriority()
196 if (!P.getSUnit()->isBoundaryNode() && !isScheduled(P.getSUnit()) && in bumpPredsPriority()
197 Set.insert(P.getSUnit()).second) in bumpPredsPriority()
198 Worklist.push_back(P.getSUnit()); in bumpPredsPriority()
215 auto SuccSU = S.getSUnit(); in releaseSuccessors()
H A DAMDGPUExportClustering.cpp70 SUnit *PredSU = Pred.getSUnit(); in buildCluster()
86 SUnit *PredSU = Pred.getSUnit(); in removeExportDependencies()
95 SUnit *ExportPredSU = ExportPred.getSUnit(); in removeExportDependencies()
130 removeExportDependencies(DAG, *Succ.getSUnit()); in apply()
H A DSIMachineScheduler.cpp425 if (BC->isSUInBlock(Succ.getSUnit(), ID)) in undoSchedule()
435 SUnit *SuccSU = SuccEdge->getSUnit(); in undoReleaseSucc()
445 SUnit *SuccSU = SuccEdge->getSUnit(); in releaseSucc()
466 SUnit *SuccSU = Succ.getSUnit(); in releaseSuccessors()
499 NodeNum2Index.find(Succ.getSUnit()->NodeNum); in nodeScheduled()
647 if (PredDep.getSUnit() == &FromSU && in hasDataDependencyPred()
802 SUnit *Pred = PredDep.getSUnit(); in colorComputeReservedDependencies()
844 SUnit *Succ = SuccDep.getSUnit(); in colorComputeReservedDependencies()
928 SUnit *Succ = SuccDep.getSUnit(); in colorEndsAccordingToDependencies()
998 SUnit *Succ = SuccDep.getSUnit(); in colorMergeConstantLoadsNextGroup()
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H A DGCNILPSched.cpp66 SUnit *PredSU = Pred.getSUnit(); in CalcNodeSethiUllmanNumber()
110 unsigned Height = Succ.getSUnit()->getHeight(); in closestSucc()
277 auto PredSU = PredEdge.getSUnit(); in releasePredecessors()
H A DAMDGPUSubtarget.cpp876 const SUnit *SU = SI.getSUnit(); in canAddEdge()
889 if (SI.getSUnit() != SU && !Visited.count(SI.getSUnit())) in canAddEdge()
890 Preds.push_back(SI.getSUnit()); in canAddEdge()
915 SUnit *SUv = SI.getSUnit(); in linkSALUChain()
921 SUnit *Succ = SI.getSUnit(); in linkSALUChain()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonSubtarget.cpp225 MachineInstr &MI2 = *SI.getSUnit()->getInstr(); in apply()
232 for (SDep &PI : SI.getSUnit()->Preds) { in apply()
233 if (PI.getSUnit() != &SU || PI.getKind() != SDep::Order) in apply()
236 SI.getSUnit()->setDepthDirty(); in apply()
419 MachineInstr *DDst = Dst->Succs[0].getSUnit()->getInstr(); in adjustSchedDependency()
492 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in restoreLatency()
540 if (!I.isAssignedRegDep() || I.getSUnit() != Dst) in changeLatency()
557 !I.getSUnit()->getInstr()->isPseudo()) in getZeroLatency()
558 return I.getSUnit(); in getZeroLatency()
635 if (ExclSrc.count(I.getSUnit()) == 0 && in isBestZeroLatency()
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H A DHexagonHazardRecognizer.cpp145 S.getSUnit()->NumPredsLeft == 1) { in EmitInstruction()
146 UsesDotCur = S.getSUnit(); in EmitInstruction()
160 TII->mayBeNewStore(*S.getSUnit()->getInstr()) && in EmitInstruction()
161 Resources->canReserveResources(*S.getSUnit()->getInstr())) { in EmitInstruction()
162 PrefVectorStoreNew = S.getSUnit(); in EmitInstruction()
H A DHexagonMachineScheduler.cpp86 if (S.getSUnit() == SUu && S.getLatency() > 0) in hasDependence()
293 unsigned PredReadyCycle = PI.getSUnit()->TopReadyCycle; in releaseTopNode()
312 unsigned SuccReadyCycle = I->getSUnit()->BotReadyCycle; in releaseBottomNode()
527 if (!Pred.getSUnit()->isScheduled && (Pred.getSUnit() != SU2)) in isSingleUnscheduledPred()
542 if (!Succ.getSUnit()->isScheduled && (Succ.getSUnit() != SU2)) in isSingleUnscheduledSucc()
647 if (isSingleUnscheduledPred(SI.getSUnit(), SU)) in SchedulingCost()
653 if (isSingleUnscheduledSucc(PI.getSUnit(), SU)) in SchedulingCost()
707 if (!PI.getSUnit()->getInstr()->isPseudo() && PI.isAssignedRegDep() && in SchedulingCost()
709 Top.ResourceModel->isInPacket(PI.getSUnit())) { in SchedulingCost()
716 if (!SI.getSUnit()->getInstr()->isPseudo() && SI.isAssignedRegDep() && in SchedulingCost()
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H A DHexagonVLIWPacketizer.cpp938 if (Dep.getSUnit() == PacketSUDep && Dep.getKind() == SDep::Anti && in restrictingDepExistInPacket()
1006 if (Dep.getSUnit() == SU && Dep.getKind() == SDep::Data && in arePredicatesComplements()
1407 if (SUJ->Succs[i].getSUnit() != SUI) in isLegalToPacketizeTogether()
1928 if (Pred.getSUnit() == SUJ) in producesStall()
1939 if (Pred.getSUnit() == SUJ && Pred.getLatency() > 1) in producesStall()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGRRList.cpp226 Topo.AddPredQueued(SU, D.getSUnit()); in AddPredQueued()
234 Topo.AddPred(SU, D.getSUnit()); in AddPred()
242 Topo.RemovePred(SU, D.getSUnit()); in RemovePred()
399 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
564 assert((!RegDef || RegDef == SU || RegDef == Pred.getSUnit()) && in ReleasePredecessors()
566 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
821 SUnit *PredSU = PredEdge->getSUnit(); in CapturePred()
843 assert(LiveRegDefs[Pred.getReg()] == Pred.getSUnit() && in UnscheduleNodeBottomUp()
899 LiveRegGens[Reg] = Succ.getSUnit(); in UnscheduleNodeBottomUp()
902 Succ2.getSUnit()->getHeight() < LiveRegGens[Reg]->getHeight()) in UnscheduleNodeBottomUp()
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H A DResourcePriorityQueue.cpp77 SUnit *PredSU = Pred.getSUnit(); in numberRCValPredInSU()
115 SUnit *SuccSU = Succ.getSUnit(); in numberRCValSuccInSU()
217 SUnit &PredSU = *Pred.getSUnit(); in getSingleUnscheduledPred()
234 if (getSingleUnscheduledPred(Succ.getSUnit()) == SU) in push()
278 if (Succ.getSUnit() == SU) in isResourceAvailable()
503 if (Pred.isCtrl() || (Pred.getSUnit()->NumRegDefsLeft == 0)) in scheduledNode()
505 --Pred.getSUnit()->NumRegDefsLeft; in scheduledNode()
518 adjustPriorityOfUnscheduledPreds(Succ.getSUnit()); in scheduledNode()
H A DScheduleDAGFast.cpp140 SUnit *PredSU = PredEdge->getSUnit(); in ReleasePred()
171 LiveRegDefs[Pred.getReg()] = Pred.getSUnit(); in ReleasePredecessors()
194 if (LiveRegCycles[Succ.getReg()] == Succ.getSUnit()->getHeight()) { in ScheduleNodeBottomUp()
285 else if (Pred.getSUnit()->getNode() && in CopyAndMoveSuccessors()
286 Pred.getSUnit()->getNode()->isOperandOf(LoadNode)) in CopyAndMoveSuccessors()
298 if (ChainPred.getSUnit()) { in CopyAndMoveSuccessors()
317 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
325 SUnit *SuccDep = D.getSUnit(); in CopyAndMoveSuccessors()
362 SUnit *SuccSU = Succ.getSUnit(); in CopyAndMoveSuccessors()
398 SUnit *SuccSU = Succ.getSUnit(); in InsertCopiesAndMoveSuccs()
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H A DScheduleDAGVLIW.cpp114 SUnit *SuccSU = D.getSUnit(); in releaseSucc()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCHazardRecognizers.cpp39 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isLoadAfterStore()
47 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isLoadAfterStore()
65 const MCInstrDesc *PredMCID = DAG->getInstrDesc(SU->Preds[i].getSUnit()); in isBCTRAfterSet()
73 if (SU->Preds[i].getSUnit() == CurGroup[j]) in isBCTRAfterSet()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DScheduleDAG.h152 SUnit *getSUnit() const;
433 if (Pred.getSUnit() == N) in isPred()
441 if (Succ.getSUnit() == N) in isSucc()
480 inline SUnit *SDep::getSUnit() const { return Dep.getPointer(); } in getSUnit() function
636 return Node->Preds[Operand].getSUnit();
H A DScheduleDAGInstrs.h286 SUnit *getSUnit(MachineInstr *MI) const;
390 inline SUnit *ScheduleDAGInstrs::getSUnit(MachineInstr *MI) const { in getSUnit() function
H A DMachinePipeliner.h243 return Source->getInstr()->isPHI() || Dep.getSUnit()->getInstr()->isPHI(); in isBackedge()
330 auto SuccSUnit = Succ.getSUnit(); in NodeSet()

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