Home
last modified time | relevance | path

Searched refs:getOrder (Results 1 – 25 of 27) sorted by relevance

12

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DScheduleDAGSDNodes.cpp760 unsigned DVOrder = DV->getOrder(); in ProcessSDDbgValues()
971 return LHS->getOrder() < RHS->getOrder(); in EmitSchedule()
984 if ((*DI)->getOrder() < LastOrder || (*DI)->getOrder() >= Order) in EmitSchedule()
1010 assert((*DI)->getOrder() >= LastOrder && in EmitSchedule()
1032 (*DLI)->getOrder() >= LastOrder && (*DLI)->getOrder() < Order; in EmitSchedule()
H A DSDNodeDbgValue.h218 unsigned getOrder() const { return Order; } in getOrder() function
258 unsigned getOrder() const { return Order; } in getOrder() function
H A DSelectionDAGDumper.cpp837 OS << " DbgVal(Order=" << getOrder() << ')'; in print()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DAllocationOrder.cpp34 auto Order = RegClassInfo.getOrder(MF.getRegInfo().getRegClass(VirtReg)); in create()
H A DAllocationOrder.h111 ArrayRef<MCPhysReg> getOrder() const { return Order; } in getOrder() function
H A DRegAllocBase.cpp128 ArrayRef<MCPhysReg> AllocOrder = RegClassInfo.getOrder(RC); in allocatePhysRegs()
H A DRegAllocFast.cpp777 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtReg()
830 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in allocVirtRegUndef()
961 ArrayRef<MCPhysReg> AllocationOrder = RegClassInfo.getOrder(&RC); in useVirtReg()
1195 unsigned ClassSize0 = RegClassInfo.getOrder(&RC0).size(); in allocateInstruction()
1196 unsigned ClassSize1 = RegClassInfo.getOrder(&RC1).size(); in allocateInstruction()
H A DBreakFalseDeps.cpp153 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(OpRC); in pickBestRegisterForUndef()
H A DRegAllocGreedy.cpp1077 for (MCRegister PhysReg : Order.getOrder()) { in getCheapestEvicteeWeight()
1161 unsigned OrderLimit = Order.getOrder().size(); in tryEvict()
1180 if (RegCosts[Order.getOrder().back()] >= CostPerUseLimit) { in tryEvict()
1588 for (auto PhysReg : Order.getOrder()) { in splitCanCauseLocalSpill()
H A DCriticalAntiDepBreaker.cpp402 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(RC); in findSuitableFreeRegister()
H A DAggressiveAntiDepBreaker.cpp624 ArrayRef<MCPhysReg> Order = RegClassInfo.getOrder(SuperRC); in FindSuitableFreeRegisters()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Passes/
H A DStandardInstrumentations.cpp574 std::vector<std::string>::const_iterator BI = Before.getOrder().begin(); in report()
575 std::vector<std::string>::const_iterator BE = Before.getOrder().end(); in report()
576 std::vector<std::string>::const_iterator AI = After.getOrder().begin(); in report()
577 std::vector<std::string>::const_iterator AE = After.getOrder().end(); in report()
697 CFD.getOrder().emplace_back(B.getName()); in generateFunctionData()
700 Data.getOrder().emplace_back(F.getName()); in generateFunctionData()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DRegisterClassInfo.h99 ArrayRef<MCPhysReg> getOrder(const TargetRegisterClass *RC) const { in getOrder() function
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Passes/
H A DStandardInstrumentations.h309 std::vector<std::string> &getOrder() { return Order; } in getOrder() function
310 const std::vector<std::string> &getOrder() const { return Order; } in getOrder() function
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DRegisterInfoEmitter.cpp1042 ArrayRef<Record*> Order = RC.getOrder(); in runMCDesc()
1084 << RegClassStrings.get(RC.getName()) << ", " << RC.getOrder().size() in runMCDesc()
1228 ArrayRef<Record*> Order = RC.getOrder(); in runTargetDesc()
1379 ArrayRef<Record*> Elems = RC.getOrder(oi); in runTargetDesc()
1392 if (RC.getOrder(oi).empty()) in runTargetDesc()
H A DCodeGenRegisters.h430 ArrayRef<Record*> getOrder(unsigned No = 0) const {
H A DAsmMatcherEmitter.cpp1223 RegisterSet(RC.getOrder().begin(), RC.getOrder().end())); in buildRegisterClasses()
1299 ClassInfo *CI = RegisterSetClasses[RegisterSet(RC.getOrder().begin(), in buildRegisterClasses()
1300 RC.getOrder().end())]; in buildRegisterClasses()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIPreAllocateWWMRegs.cpp103 for (MCRegister PhysReg : RegClassInfo.getOrder(MRI->getRegClass(Reg))) { in processDef()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64A57FPLoadBalancing.cpp519 auto Ord = RCI.getOrder(TRI->getRegClass(RegClassID)); in scavengeRegister()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMLowOverheadLoops.cpp122 const SmallVectorImpl<MachineBasicBlock*> &getOrder() const { in getOrder() function in __anonf568b4ed0111::PostOrderLoopTraversal
1645 const SmallVectorImpl<MachineBasicBlock*> &PostOrder = DFS.getOrder(); in Expand()
H A DARMLoadStoreOptimizer.cpp589 for (unsigned Reg : RegClassInfo.getOrder(&RegClass)) in findFreeReg()
/netbsd-src/external/apache2/llvm/dist/clang/lib/CodeGen/
H A DCGOpenMPRuntime.h530 unsigned getOrder() const { return Order; } in getOrder() function
H A DCGOpenMPRuntime.cpp3192 GetMDInt(Line), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
3206 OrderedEntries[E.getOrder()] = std::make_tuple(&E, Loc, ParentName); in createOffloadEntriesAndInfoMetadata()
3207 ParentFunctions[E.getOrder()] = ParentName; in createOffloadEntriesAndInfoMetadata()
3231 GetMDInt(E.getFlags()), GetMDInt(E.getOrder())}; in createOffloadEntriesAndInfoMetadata()
3234 OrderedEntries[E.getOrder()] = in createOffloadEntriesAndInfoMetadata()
3251 StringRef FnName = ParentFunctions[CE->getOrder()]; in createOffloadEntriesAndInfoMetadata()
H A DCGAtomic.cpp829 llvm::Value *Order = EmitScalarExpr(E->getOrder()); in EmitAtomicExpr()
/netbsd-src/external/apache2/llvm/dist/clang/lib/AST/
H A DStmtPrinter.cpp1674 PrintExpr(Node->getOrder()); in VisitAtomicExpr()

12