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Searched refs:getOperand (Results 1 – 25 of 957) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/MCTargetDesc/
H A DX86InstComments.cpp251 unsigned OpReg = MI->getOperand(OperandIndex).getReg(); in getRegOperandNumElts()
274 const char *MaskRegName = getRegName(MI->getOperand(MaskOp).getReg()); in printMasking()
312 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
316 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
317 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
321 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
322 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
327 AccName = getRegName(MI->getOperand(NumOperands - 1).getReg()); in printFMAComments()
331 Mul2Name = getRegName(MI->getOperand(2).getReg()); in printFMAComments()
332 Mul1Name = getRegName(MI->getOperand(1).getReg()); in printFMAComments()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp36 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
40 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(0).getReg())) in lowerRILow()
41 .addReg(SystemZMC::getRegAsGR32(MI->getOperand(1).getReg())) in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
50 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
54 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(0).getReg())) in lowerRIHigh()
55 .addReg(SystemZMC::getRegAsGRH32(MI->getOperand(1).getReg())) in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/
H A DPPCMIPeephole.cpp174 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
177 MI->getOperand(3).getImm() <= 63 - MI->getOperand(2).getImm()) in getKnownLeadingZeroCount()
178 return MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
183 MI->getOperand(3).getImm() <= MI->getOperand(4).getImm()) in getKnownLeadingZeroCount()
184 return 32 + MI->getOperand(3).getImm(); in getKnownLeadingZeroCount()
187 uint16_t Imm = MI->getOperand(2).getImm(); in getKnownLeadingZeroCount()
287 Register RegOp = VisitedPHI->getOperand(PHIOp).getReg(); in collectUnprimedAccPHIs()
295 Register Reg = Instr->getOperand(1).getReg(); in collectUnprimedAccPHIs()
334 Register RegOp = PHI->getOperand(PHIOp).getReg(); in convertUnprimedAccPHIs()
341 assert(MRI->getRegClass(PHIInput->getOperand(1).getReg()) == in convertUnprimedAccPHIs()
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H A DPPCVSXFMAMutate.cpp112 LIS->getInterval(MI.getOperand(1).getReg()).Query(FMAIdx).valueIn(); in processBlock()
130 Register AddendSrcReg = AddendMI->getOperand(1).getReg(); in processBlock()
132 if (MRI.getRegClass(AddendMI->getOperand(0).getReg()) != in processBlock()
138 if (!MRI.getRegClass(AddendMI->getOperand(0).getReg()) in processBlock()
164 if (J->readsVirtualRegister(AddendMI->getOperand(0).getReg())) { in processBlock()
186 Register OldFMAReg = MI.getOperand(0).getReg(); in processBlock()
190 Register Reg2 = MI.getOperand(2).getReg(); in processBlock()
191 Register Reg3 = MI.getOperand(3).getReg(); in processBlock()
218 Register KilledProdReg = MI.getOperand(KilledProdOp).getReg(); in processBlock()
219 Register OtherProdReg = MI.getOperand(OtherProdOp).getReg(); in processBlock()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AVR/
H A DAVRExpandPseudoInsts.cpp145 Register DstReg = MI.getOperand(0).getReg(); in expandArith()
146 Register SrcReg = MI.getOperand(2).getReg(); in expandArith()
147 bool DstIsDead = MI.getOperand(0).isDead(); in expandArith()
148 bool DstIsKill = MI.getOperand(1).isKill(); in expandArith()
149 bool SrcIsKill = MI.getOperand(2).isKill(); in expandArith()
150 bool ImpIsDead = MI.getOperand(3).isDead(); in expandArith()
165 MIBHI->getOperand(3).setIsDead(); in expandArith()
168 MIBHI->getOperand(4).setIsKill(); in expandArith()
178 Register DstReg = MI.getOperand(0).getReg(); in expandLogic()
179 Register SrcReg = MI.getOperand(2).getReg(); in expandLogic()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp100 const MCOperand &Dst = MI->getOperand(0); in printInst()
101 const MCOperand &MO1 = MI->getOperand(1); in printInst()
102 const MCOperand &MO2 = MI->getOperand(2); in printInst()
103 const MCOperand &MO3 = MI->getOperand(3); in printInst()
123 const MCOperand &Dst = MI->getOperand(0); in printInst()
124 const MCOperand &MO1 = MI->getOperand(1); in printInst()
125 const MCOperand &MO2 = MI->getOperand(2); in printInst()
150 if (MI->getOperand(0).getReg() == ARM::SP && MI->getNumOperands() > 5) { in printInst()
164 if (MI->getOperand(2).getReg() == ARM::SP && in printInst()
165 MI->getOperand(3).getImm() == -4) { in printInst()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp78 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::COUNT)) in getCFAluSize()
85 .getOperand(TII->getOperandIdx(MI.getOpcode(), R600::OpName::Enabled)) in isCFAluEnabled()
102 CFAlu.getOperand(CntIdx).setImm(getCFAluSize(CFAlu) + getCFAluSize(MI)); in cleanPotentialDisabledCFAlu()
127 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
128 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
130 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
131 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
132 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
143 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp57 const MCOperand &MO = MI->getOperand(OpNum); in printOperand()
89 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
90 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
95 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
96 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
97 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
98 if (MI->getOperand(OpNum + 2).isImm() && in printMemASXOperand()
99 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
106 if (MI->getOperand(OpNum + 1).isImm() && in printMemASXOperand()
107 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/
H A DRISCVMergeBaseOffset.cpp83 HiLUI.getOperand(1).getTargetFlags() != RISCVII::MO_HI || in INITIALIZE_PASS()
84 HiLUI.getOperand(1).getType() != MachineOperand::MO_GlobalAddress || in INITIALIZE_PASS()
85 HiLUI.getOperand(1).getOffset() != 0 || in INITIALIZE_PASS()
86 !MRI->hasOneUse(HiLUI.getOperand(0).getReg())) in INITIALIZE_PASS()
88 Register HiLuiDestReg = HiLUI.getOperand(0).getReg(); in INITIALIZE_PASS()
91 LoADDI->getOperand(2).getTargetFlags() != RISCVII::MO_LO || in INITIALIZE_PASS()
92 LoADDI->getOperand(2).getType() != MachineOperand::MO_GlobalAddress || in INITIALIZE_PASS()
93 LoADDI->getOperand(2).getOffset() != 0 || in INITIALIZE_PASS()
94 !MRI->hasOneUse(LoADDI->getOperand(0).getReg())) in INITIALIZE_PASS()
106 HiLUI.getOperand(1).setOffset(Offset); in foldOffset()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/XCore/
H A DXCoreISelDAGToDAG.cpp97 if ((FIN = dyn_cast<FrameIndexSDNode>(Addr.getOperand(0))) in SelectADDRspii()
98 && (CN = dyn_cast<ConstantSDNode>(Addr.getOperand(1))) in SelectADDRspii()
128 OutOps.push_back(Op.getOperand(0)); in SelectInlineAsmMemoryOperand()
163 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
164 N->getOperand(2) }; in Select()
170 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
171 N->getOperand(2) }; in Select()
177 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
178 N->getOperand(2), N->getOperand(3) }; in Select()
184 SDValue Ops[] = { N->getOperand(0), N->getOperand(1), in Select()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/MCTargetDesc/
H A DMipsMCCodeEmitter.cpp62 assert(Inst.getOperand(2).isImm()); in LowerLargeShift()
64 int64_t Shift = Inst.getOperand(2).getImm(); in LowerLargeShift()
70 Inst.getOperand(2).setImm(Shift); in LowerLargeShift()
95 unsigned RegOp0 = Inst.getOperand(0).getReg(); in LowerCompactBranch()
96 unsigned RegOp1 = Inst.getOperand(1).getReg(); in LowerCompactBranch()
116 Inst.getOperand(0).setReg(RegOp1); in LowerCompactBranch()
117 Inst.getOperand(1).setReg(RegOp0); in LowerCompactBranch()
239 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue()
261 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValue1SImm16()
283 const MCOperand &MO = MI.getOperand(OpNo); in getBranchTargetOpValueMMR6()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/MCTargetDesc/
H A DHexagonMCCompound.cpp97 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
98 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
99 Src2Reg = MI.getOperand(2).getReg(); in getCompoundCandidateGroup()
111 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
112 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
123 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
124 SrcReg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
133 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
142 DstReg = MI.getOperand(0).getReg(); in getCompoundCandidateGroup()
143 Src1Reg = MI.getOperand(1).getReg(); in getCompoundCandidateGroup()
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H A DHexagonMCDuplexInfo.cpp201 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
202 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
219 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
220 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
240 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
241 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
250 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
251 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
260 DstReg = MCI.getOperand(0).getReg(); in getDuplexCandidateGroup()
261 SrcReg = MCI.getOperand(1).getReg(); in getDuplexCandidateGroup()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DGISelKnownBits.cpp38 return computeKnownAlignment(MI->getOperand(1).getReg(), Depth); in computeKnownAlignment()
40 int FrameIdx = MI->getOperand(1).getIndex(); in computeKnownAlignment()
53 return getKnownBits(MI.getOperand(0).getReg()); in getKnownBits()
171 computeKnownBitsImpl(MI.getOperand(i + 1).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
191 assert(MI.getOperand(0).getSubReg() == 0 && "Is this code in SSA?"); in computeKnownBitsImpl()
205 const MachineOperand &Src = MI.getOperand(Idx); in computeKnownBitsImpl()
240 int FrameIdx = MI.getOperand(1).getIndex(); in computeKnownBitsImpl()
245 computeKnownBitsImpl(MI.getOperand(1).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
247 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known2, DemandedElts, in computeKnownBitsImpl()
254 computeKnownBitsImpl(MI.getOperand(2).getReg(), Known, DemandedElts, in computeKnownBitsImpl()
[all …]
H A DCombinerHelper.cpp154 Register DstReg = MI.getOperand(0).getReg(); in matchCombineCopy()
155 Register SrcReg = MI.getOperand(1).getReg(); in matchCombineCopy()
159 Register DstReg = MI.getOperand(0).getReg(); in applyCombineCopy()
160 Register SrcReg = MI.getOperand(1).getReg(); in applyCombineCopy()
204 assert(MRI.getType(Undef->getOperand(0).getReg()) == in matchCombineConcatVectors()
211 Ops.push_back(Undef->getOperand(0).getReg()); in matchCombineConcatVectors()
224 Register DstReg = MI.getOperand(0).getReg(); in applyCombineConcatVectors()
255 LLT DstType = MRI.getType(MI.getOperand(0).getReg()); in matchCombineShuffleVector()
256 Register Src1 = MI.getOperand(1).getReg(); in matchCombineShuffleVector()
292 ArrayRef<int> Mask = MI.getOperand(3).getShuffleMask(); in matchCombineShuffleVector()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64ExpandPseudoInsts.cpp107 const MachineOperand &MO = OldMI.getOperand(i); in transferImpOps()
122 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
124 MI.getOperand(0).isRenamable() ? RegState::Renamable : 0; in expandMOVImm()
125 uint64_t Imm = MI.getOperand(1).getImm(); in expandMOVImm()
148 .add(MI.getOperand(0)) in expandMOVImm()
156 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
166 Register DstReg = MI.getOperand(0).getReg(); in expandMOVImm()
167 bool DstIsDead = MI.getOperand(0).isDead(); in expandMOVImm()
190 const MachineOperand &Dest = MI.getOperand(0); in expandCMP_SWAP()
191 Register StatusReg = MI.getOperand(1).getReg(); in expandCMP_SWAP()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonInstrInfo.cpp178 if (Opc == EndLoopOp && I->getOperand(0).getMBB() != TargetBB) in findLoopInstr()
197 const MachineOperand &MO = MI.getOperand(i); in parseOperands()
260 const MachineOperand OpFI = MI.getOperand(1); in isLoadFromStackSlot()
263 const MachineOperand OpOff = MI.getOperand(2); in isLoadFromStackSlot()
267 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
274 const MachineOperand OpFI = MI.getOperand(2); in isLoadFromStackSlot()
277 const MachineOperand OpOff = MI.getOperand(3); in isLoadFromStackSlot()
281 return MI.getOperand(0).getReg(); in isLoadFromStackSlot()
308 const MachineOperand &OpFI = MI.getOperand(0); in isStoreToStackSlot()
311 const MachineOperand &OpOff = MI.getOperand(1); in isStoreToStackSlot()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DDAGCombiner.cpp895 LHS = N.getOperand(0); in isSetCCEquivalent()
896 RHS = N.getOperand(1); in isSetCCEquivalent()
897 CC = N.getOperand(2); in isSetCCEquivalent()
904 LHS = N.getOperand(1); in isSetCCEquivalent()
905 RHS = N.getOperand(2); in isSetCCEquivalent()
906 CC = N.getOperand(3); in isSetCCEquivalent()
911 !TLI.isConstTrueVal(N.getOperand(2).getNode()) || in isSetCCEquivalent()
912 !TLI.isConstFalseVal(N.getOperand(3).getNode())) in isSetCCEquivalent()
919 LHS = N.getOperand(0); in isSetCCEquivalent()
920 RHS = N.getOperand(1); in isSetCCEquivalent()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DMVETPAndVPTOptimisationsPass.cpp98 MI->getOperand(1).getReg().isVirtual()) in INITIALIZE_PASS_DEPENDENCY()
99 MI = MRI->getVRegDef(MI->getOperand(1).getReg()); in INITIALIZE_PASS_DEPENDENCY()
119 if (T.getOpcode() == ARM::t2LoopEnd && T.getOperand(1).getMBB() == Header) { in findLoopComponents()
124 T.getOperand(2).getMBB() == Header) { in findLoopComponents()
148 LookThroughCOPY(MRI->getVRegDef(LoopEnd->getOperand(0).getReg()), MRI); in findLoopComponents()
157 LookThroughCOPY(MRI->getVRegDef(LoopDec->getOperand(1).getReg()), MRI); in findLoopComponents()
160 (LoopPhi->getOperand(2).getMBB() != Latch && in findLoopComponents()
161 LoopPhi->getOperand(4).getMBB() != Latch)) { in findLoopComponents()
167 Register StartReg = LoopPhi->getOperand(2).getMBB() == Latch in findLoopComponents()
168 ? LoopPhi->getOperand(3).getReg() in findLoopComponents()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Mips/
H A DMipsSEISelLowering.cpp419 SDValue Tmp = DAG.getNode(MipsISD::MTC1_D64, DL, MVT::f64, Op->getOperand(0)); in lowerSELECT()
420 return DAG.getNode(MipsISD::FSELECT, DL, ResTy, Tmp, Op->getOperand(1), in lowerSELECT()
421 Op->getOperand(2)); in lowerSELECT()
488 SDValue Op0 = N->getOperand(0); in performANDCombine()
489 SDValue Op1 = N->getOperand(1); in performANDCombine()
508 SDValue Op0Op2 = Op0->getOperand(2); in performANDCombine()
515 SDValue Ops[] = { Op0->getOperand(0), Op0->getOperand(1), Op0Op2 }; in performANDCombine()
558 N = N->getOperand(0); in isVectorAllOnes()
582 if (isVectorAllOnes(N->getOperand(0))) in isBitwiseInverse()
583 return N->getOperand(1) == OfNode; in isBitwiseInverse()
[all …]
H A DMipsInstructionSelector.cpp107 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
184 const Register ValueReg = I.getOperand(0).getReg(); in selectLoadStoreOpCode()
262 .add(I.getOperand(0)) in buildUnalignedStore()
300 isRegInGprb(I.getOperand(0).getReg(), MRI)) { in select()
302 .add(I.getOperand(0)) in select()
303 .add(I.getOperand(1)) in select()
304 .add(I.getOperand(2)); in select()
307 Mul->getOperand(3).setIsDead(true); in select()
308 Mul->getOperand(4).setIsDead(true); in select()
327 .add(I.getOperand(1)) in select()
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H A DMicroMipsSizeReduction.cpp310 if (!MI->getOperand(Op).isImm()) in GetImm()
312 Imm = MI->getOperand(Op).getImm(); in GetImm()
364 Register reg = MI->getOperand(0).getReg(); in CheckXWPInstr()
371 if (ReduceToLwp && (MI->getOperand(0).getReg() == MI->getOperand(1).getReg())) in CheckXWPInstr()
406 Register Reg1 = MI1->getOperand(0).getReg(); in ConsecutiveInstr()
407 Register Reg2 = MI2->getOperand(0).getReg(); in ConsecutiveInstr()
448 if (!IsSP(MI->getOperand(1))) in ReduceXWtoXWSP()
478 Register Reg1 = MI1->getOperand(1).getReg(); in ReduceXWtoXWP()
479 Register Reg2 = MI2->getOperand(1).getReg(); in ReduceXWtoXWP()
500 if (!isMMThreeBitGPRegister(MI->getOperand(0)) || in ReduceArithmeticInstructions()
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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
77 << getRegisterName(MI->getOperand(1).getReg()) << "], %" in printMemoryLoadIncrement()
78 << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
83 << getRegisterName(MI->getOperand(1).getReg()) << decIncOperator(MI) in printMemoryLoadIncrement()
84 << "], %" << getRegisterName(MI->getOperand(0).getReg()); in printMemoryLoadIncrement()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64InstructionSelector.cpp622 LLT Ty = MRI.getType(I.getOperand(0).getReg()); in unsupportedBinOp()
775 const Register DstReg = I.getOperand(0).getReg(); in isValidCopy()
776 const Register SrcReg = I.getOperand(1).getReg(); in isValidCopy()
814 MachineOperand &RegOp = I.getOperand(1); in copySubReg()
819 if (!Register::isPhysicalRegister(I.getOperand(0).getReg())) in copySubReg()
820 RBI.constrainGenericRegister(I.getOperand(0).getReg(), *To, MRI); in copySubReg()
833 Register DstReg = I.getOperand(0).getReg(); in getRegClassesForCopy()
834 Register SrcReg = I.getOperand(1).getReg(); in getRegClassesForCopy()
858 Register DstReg = I.getOperand(0).getReg(); in selectCopy()
859 Register SrcReg = I.getOperand(1).getReg(); in selectCopy()
[all …]
H A DAArch64PostLegalizerLowering.cpp221 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask(); in matchREV()
222 Register Dst = MI.getOperand(0).getReg(); in matchREV()
223 Register Src = MI.getOperand(1).getReg(); in matchREV()
251 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask(); in matchTRN()
252 Register Dst = MI.getOperand(0).getReg(); in matchTRN()
257 Register V1 = MI.getOperand(1).getReg(); in matchTRN()
258 Register V2 = MI.getOperand(2).getReg(); in matchTRN()
272 ArrayRef<int> ShuffleMask = MI.getOperand(3).getShuffleMask(); in matchUZP()
273 Register Dst = MI.getOperand(0).getReg(); in matchUZP()
278 Register V1 = MI.getOperand(1).getReg(); in matchUZP()
[all …]

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