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Searched refs:getNamedOperand (Results 1 – 23 of 23) sorted by relevance

/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIPeepholeSDWA.cpp308 if (TII->getNamedOperand(*MI, AMDGPU::OpName::src0) == SrcOp) { in getSrcMods()
309 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src0_modifiers)) { in getSrcMods()
312 } else if (TII->getNamedOperand(*MI, AMDGPU::OpName::src1) == SrcOp) { in getSrcMods()
313 if (auto *Mod = TII->getNamedOperand(*MI, AMDGPU::OpName::src1_modifiers)) { in getSrcMods()
343 MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in convertToSDWA()
344 MachineOperand *SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src0_sel); in convertToSDWA()
346 TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers); in convertToSDWA()
350 Src = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in convertToSDWA()
351 SrcSel = TII->getNamedOperand(MI, AMDGPU::OpName::src1_sel); in convertToSDWA()
352 SrcMods = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers); in convertToSDWA()
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H A DGCNDPPCombine.cpp126 if (const auto *SDst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in isShrinkable()
201 auto *Dst = TII->getNamedOperand(OrigMI, AMDGPU::OpName::vdst); in createDPPInst()
212 TII->getNamedOperand(MovMI, AMDGPU::OpName::vdst)->getReg()), in createDPPInst()
226 if (auto *Mod0 = TII->getNamedOperand(OrigMI, in createDPPInst()
238 auto *Src0 = TII->getNamedOperand(MovMI, AMDGPU::OpName::src0); in createDPPInst()
249 if (auto *Mod1 = TII->getNamedOperand(OrigMI, in createDPPInst()
261 if (auto *Src1 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src1)) { in createDPPInst()
271 if (auto *Src2 = TII->getNamedOperand(OrigMI, AMDGPU::OpName::src2)) { in createDPPInst()
272 if (!TII->getNamedOperand(*DPPInst.getInstr(), AMDGPU::OpName::src2) || in createDPPInst()
281 DPPInst.add(*TII->getNamedOperand(MovMI, AMDGPU::OpName::dpp_ctrl)); in createDPPInst()
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H A DSILoadStoreOptimizer.cpp292 TII.getNamedOperand(MI, AMDGPU::OpName::dmask)->getImm(); in getOpcodeWidth()
517 DMask = TII.getNamedOperand(*I, AMDGPU::OpName::dmask)->getImm(); in setMI()
526 Format = TII.getNamedOperand(*I, AMDGPU::OpName::format)->getImm(); in setMI()
533 CPol = TII.getNamedOperand(*I, AMDGPU::OpName::cpol)->getImm(); in setMI()
676 const auto *TFEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::tfe); in dmasksCanBeCombined()
677 const auto *LWEOp = TII.getNamedOperand(*CI.I, AMDGPU::OpName::lwe); in dmasksCanBeCombined()
873 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::vdst)) { in getDataRegClass()
876 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::vdata)) { in getDataRegClass()
879 if (const auto *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) { in getDataRegClass()
882 if (const auto *Dst = TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) { in getDataRegClass()
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H A DSIOptimizeExecMaskingPreRA.cpp155 MachineOperand *Op1 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
156 MachineOperand *Op2 = TII->getNamedOperand(*Cmp, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
171 Op1 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src0); in optimizeVcndVcmpPair()
172 Op2 = TII->getNamedOperand(*Sel, AMDGPU::OpName::src1); in optimizeVcndVcmpPair()
173 MachineOperand *CC = TII->getNamedOperand(*Sel, AMDGPU::OpName::src2); in optimizeVcndVcmpPair()
H A DSIInstrInfo.cpp257 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::addr); in getMemOperandsWithOffsetWidth()
258 OffsetOp = getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
278 getNamedOperand(LdSt, AMDGPU::OpName::offset0); in getMemOperandsWithOffsetWidth()
280 getNamedOperand(LdSt, AMDGPU::OpName::offset1); in getMemOperandsWithOffsetWidth()
319 const MachineOperand *RSrc = getNamedOperand(LdSt, AMDGPU::OpName::srsrc); in getMemOperandsWithOffsetWidth()
323 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::vaddr); in getMemOperandsWithOffsetWidth()
327 getNamedOperand(LdSt, AMDGPU::OpName::offset); in getMemOperandsWithOffsetWidth()
330 getNamedOperand(LdSt, AMDGPU::OpName::soffset); in getMemOperandsWithOffsetWidth()
354 BaseOps.push_back(getNamedOperand(LdSt, AMDGPU::OpName::vaddr)); in getMemOperandsWithOffsetWidth()
364 BaseOp = getNamedOperand(LdSt, AMDGPU::OpName::sbase); in getMemOperandsWithOffsetWidth()
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H A DSIFoldOperands.cpp652 if (TII->getNamedOperand(*UseMI, AMDGPU::OpName::srsrc)->getReg() != in foldOperand()
659 *TII->getNamedOperand(*UseMI, AMDGPU::OpName::soffset); in foldOperand()
1158 MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in tryFoldCndMask()
1159 MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in tryFoldCndMask()
1313 if (!TII->getNamedOperand(MI, AMDGPU::OpName::clamp)->getImm()) in isClamp()
1317 const MachineOperand *Src0 = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in isClamp()
1318 const MachineOperand *Src1 = TII->getNamedOperand(MI, AMDGPU::OpName::src1); in isClamp()
1330 = TII->getNamedOperand(MI, AMDGPU::OpName::src0_modifiers)->getImm(); in isClamp()
1332 = TII->getNamedOperand(MI, AMDGPU::OpName::src1_modifiers)->getImm(); in isClamp()
1359 MachineOperand *DefClamp = TII->getNamedOperand(*Def, AMDGPU::OpName::clamp); in tryFoldClamp()
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H A DSIRegisterInfo.cpp739 TII->getNamedOperand(MI, IsFlat ? AMDGPU::OpName::saddr in resolveFrameIndex()
742 MachineOperand *OffsetOp = TII->getNamedOperand(MI, AMDGPU::OpName::offset); in resolveFrameIndex()
758 MachineOperand *SOffset = TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in resolveFrameIndex()
964 const MachineOperand *Reg = TII->getNamedOperand(*MI, AMDGPU::OpName::vdata); in buildMUBUFOffsetLoadStore()
971 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::srsrc)) in buildMUBUFOffsetLoadStore()
972 .add(*TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)) in buildMUBUFOffsetLoadStore()
979 const MachineOperand *VDataIn = TII->getNamedOperand(*MI, in buildMUBUFOffsetLoadStore()
1565 const MachineOperand *VData = TII->getNamedOperand(*MI, in eliminateFrameIndex()
1567 assert(TII->getNamedOperand(*MI, AMDGPU::OpName::soffset)->getReg() == in eliminateFrameIndex()
1575 TII->getNamedOperand(*MI, AMDGPU::OpName::offset)->getImm(), in eliminateFrameIndex()
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H A DAMDGPUMacroFusion.cpp46 const MachineOperand *Src2 = TII.getNamedOperand(SecondMI, in shouldScheduleAdjacent()
H A DGCNHazardRecognizer.cpp142 const MachineOperand *RegOp = TII->getNamedOperand(RegInstr, in getHWReg()
730 TII->getNamedOperand(MI, AMDGPU::OpName::soffset); in createsVALUHazard()
831 TII->getNamedOperand(*RWLane, AMDGPU::OpName::src1); in checkRWLaneHazards()
896 auto *Src0 = TII->getNamedOperand(*MI, AMDGPU::OpName::src0); in fixVcmpxPermlaneHazards()
974 const MachineOperand *SDST = TII->getNamedOperand(*MI, SDSTName); in fixSMEMtoVectorWriteHazards()
1055 if (TII->getNamedOperand(MI, AMDGPU::OpName::sdst)) in fixVcmpxExecWARHazard()
1145 const auto *Offset = TII->getNamedOperand(*MI, AMDGPU::OpName::offset); in checkNSAtoVMEMHazard()
1343 Register Reg = TII.getNamedOperand(MI, AMDGPU::OpName::src2)->getReg(); in checkMAIHazards908()
1767 TII.getNamedOperand(MI, AMDGPU::OpName::src2); in checkMAIVALUHazards()
H A DSIModeRegister.cpp241 unsigned Dst = TII->getNamedOperand(MI, AMDGPU::OpName::simm16)->getImm(); in processBlockPhase1()
263 unsigned Val = TII->getNamedOperand(MI, AMDGPU::OpName::imm)->getImm(); in processBlockPhase1()
H A DSILowerSGPRSpills.cpp360 TII->getNamedOperand(MI, AMDGPU::OpName::vdata)->getReg(); in runOnMachineFunction()
378 int FI = TII->getNamedOperand(MI, AMDGPU::OpName::addr)->getIndex(); in runOnMachineFunction()
H A DAMDGPUExportClustering.cpp35 unsigned Imm = TII->getNamedOperand(*MI, AMDGPU::OpName::tgt)->getImm(); in isPositionExport()
H A DSIShrinkInstructions.cpp758 TII->getNamedOperand(MI, AMDGPU::OpName::src2); in runOnMachineFunction()
771 const MachineOperand *SDst = TII->getNamedOperand(MI, in runOnMachineFunction()
775 const MachineOperand *Src2 = TII->getNamedOperand(MI, in runOnMachineFunction()
H A DSIInsertWaitcnts.cpp626 MachineOperand *MO = TII->getNamedOperand(Inst, AMDGPU::OpName::data); in updateByEvent()
845 TII->getNamedOperand(*II, AMDGPU::OpName::simm16)->getImm(); in applyPreexistingWaitcnt()
885 TII->getNamedOperand(*WaitcntVsCntInstr, AMDGPU::OpName::simm16) in applyPreexistingWaitcnt()
888 TII->getNamedOperand(*WaitcntVsCntInstr, AMDGPU::OpName::simm16) in applyPreexistingWaitcnt()
1348 unsigned Imm = TII->getNamedOperand(Inst, AMDGPU::OpName::tgt)->getImm(); in updateEventWaitcntAfter()
H A DSIInstrInfo.h975 MachineOperand *getNamedOperand(MachineInstr &MI, unsigned OperandName) const;
978 const MachineOperand *getNamedOperand(const MachineInstr &MI, in getNamedOperand() function
980 return getNamedOperand(const_cast<MachineInstr &>(MI), OpName); in getNamedOperand()
H A DSIPreEmitPeephole.cpp227 MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::src0); in optimizeSetGPR()
H A DSIFixSGPRCopies.cpp311 TII->getNamedOperand(*MoveImm, AMDGPU::OpName::src0); in isSafeToFoldImmIntoCopy()
H A DSILowerControlFlow.cpp565 = TII->getNamedOperand(*Next, AMDGPU::OpName::src1)->getReg(); in optimizeEndCf()
H A DSIISelLowering.cpp3454 if (MachineOperand *Src = TII->getNamedOperand(MI, AMDGPU::OpName::data0)) in emitGWSMemViolTestLoop()
3612 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in loadM0FromVGPR()
3655 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in setM0ToIndexFromSGPR()
3675 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in getIndirectSGPRIdx()
3696 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in emitIndirectSrc()
3697 Register SrcReg = TII->getNamedOperand(MI, AMDGPU::OpName::src)->getReg(); in emitIndirectSrc()
3698 int Offset = TII->getNamedOperand(MI, AMDGPU::OpName::offset)->getImm(); in emitIndirectSrc()
3782 const MachineOperand *SrcVec = TII->getNamedOperand(MI, AMDGPU::OpName::src); in emitIndirectDst()
3783 const MachineOperand *Idx = TII->getNamedOperand(MI, AMDGPU::OpName::idx); in emitIndirectDst()
3784 const MachineOperand *Val = TII->getNamedOperand(MI, AMDGPU::OpName::val); in emitIndirectDst()
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H A DSIMemoryLegalizer.cpp765 MachineOperand *CPol = TII->getNamedOperand(*MI, AMDGPU::OpName::cpol); in enableNamedBit()
H A DAMDGPUAsmPrinter.cpp1004 = TII->getNamedOperand(MI, AMDGPU::OpName::callee); in analyzeResourceUsage()
/netbsd-src/external/apache2/llvm/dist/clang/lib/AST/
H A DStmt.cpp570 int GCCAsmStmt::getNamedOperand(StringRef SymbolicName) const { in getNamedOperand() function in GCCAsmStmt
740 int N = getNamedOperand(SymbolicName); in AnalyzeAsmString()
/netbsd-src/external/apache2/llvm/dist/clang/include/clang/AST/
H A DStmt.h3178 int getNamedOperand(StringRef SymbolicName) const;