Searched refs:getMaxNumSGPRs (Results 1 – 6 of 6) sorted by relevance
| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | GCNSubtarget.h | 1027 unsigned getMaxNumSGPRs(unsigned WavesPerEU, bool Addressable) const { in getMaxNumSGPRs() function
1028 return AMDGPU::IsaInfo::getMaxNumSGPRs(this, WavesPerEU, Addressable); in getMaxNumSGPRs()
1042 unsigned getMaxNumSGPRs(const MachineFunction &MF) const;
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| H A D | AMDGPUSubtarget.cpp | 730 unsigned GCNSubtarget::getMaxNumSGPRs(const MachineFunction &MF) const { in getMaxNumSGPRs() function in GCNSubtarget
737 unsigned MaxNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, false); in getMaxNumSGPRs()
738 unsigned MaxAddressableNumSGPRs = getMaxNumSGPRs(WavesPerEU.first, true); in getMaxNumSGPRs()
763 if (Requested && Requested > getMaxNumSGPRs(WavesPerEU.first, false)) in getMaxNumSGPRs()
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| H A D | SIRegisterInfo.cpp | 438 unsigned BaseIdx = alignDown(ST.getMaxNumSGPRs(MF), 4) - 4; in reservedPrivateSegmentBufferReg()
497 unsigned MaxNumSGPRs = ST.getMaxNumSGPRs(MF); in getReservedRegs()
2293 return std::min(ST.getMaxNumSGPRs(Occupancy, true), ST.getMaxNumSGPRs(MF)); in getRegPressureLimit()
2481 ST.getMaxNumSGPRs(MF) / 4); in getAllSGPR128()
2487 ST.getMaxNumSGPRs(MF) / 2); in getAllSGPR64()
2492 return makeArrayRef(AMDGPU::SGPR_32RegClass.begin(), ST.getMaxNumSGPRs(MF)); in getAllSGPR32()
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| H A D | GCNSchedStrategy.cpp | 44 SGPRCriticalLimit = ST.getMaxNumSGPRs(TargetOccupancy, true); in initialize()
389 unsigned MaxSGPRs = ST.getMaxNumSGPRs(MF); in schedule()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/Utils/ |
| H A D | AMDGPUBaseInfo.h | 217 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU,
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| H A D | AMDGPUBaseInfo.cpp | 640 unsigned getMaxNumSGPRs(const MCSubtargetInfo *STI, unsigned WavesPerEU, in getMaxNumSGPRs() function
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