| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/ |
| H A D | TargetSchedule.cpp | 205 unsigned InstrLatency = TII->getInstrLatency(&InstrItins, *DefMI); in computeOperandLatency()
279 return TII->getInstrLatency(&InstrItins, *MI); in computeInstrLatency()
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| H A D | TargetInstrInfo.cpp | 1105 int TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in TargetInstrInfo
1151 unsigned TargetInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in TargetInstrInfo
1274 return getInstrLatency(ItinData, DefMI); in computeDefOperandLatency()
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| H A D | TwoAddressInstructionPass.cpp | 763 if (TII->getInstrLatency(InstrItins, *MI) > 1) in rescheduleMIBelowKill()
896 if (TII->getInstrLatency(InstrItins, DefMI) > (Dist - DefDist)) in isDefTooClose()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/ |
| H A D | R600InstrInfo.h | 208 unsigned int getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | AMDGPUSubtarget.cpp | 830 Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *I); in adjustSchedDependency()
840 unsigned Lat = InstrInfo.getInstrLatency(getInstrItineraryData(), *DefI); in adjustSchedDependency()
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| H A D | SIInstrInfo.h | 1110 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | R600InstrInfo.cpp | 987 unsigned int R600InstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in R600InstrInfo
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| H A D | SIInstrInfo.cpp | 7818 unsigned SIInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in SIInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/ |
| H A D | ARMBaseInstrInfo.h | 452 unsigned getInstrLatency(const InstrItineraryData *ItinData,
456 int getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | ARMBaseInstrInfo.cpp | 4382 unsigned Latency = getInstrLatency(ItinData, DefMI); in getOperandLatencyImpl()
4704 unsigned ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in ARMBaseInstrInfo
4719 Latency += getInstrLatency(ItinData, *I, PredCost); in getInstrLatency()
4755 int ARMBaseInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in ARMBaseInstrInfo
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| /netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/ |
| H A D | TargetInstrInfo.h | 1601 virtual unsigned getInstrLatency(const InstrItineraryData *ItinData,
1607 virtual int getInstrLatency(const InstrItineraryData *ItinData,
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/ |
| H A D | HexagonInstrInfo.h | 278 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | HexagonInstrInfo.cpp | 1882 unsigned HexagonInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in HexagonInstrInfo
4205 return getInstrLatency(ItinData, MI); in getInstrTimingClassLatency()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/ |
| H A D | PPCInstrInfo.h | 311 unsigned getInstrLatency(const InstrItineraryData *ItinData,
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| H A D | PPCInstrInfo.cpp | 136 unsigned PPCInstrInfo::getInstrLatency(const InstrItineraryData *ItinData, in getInstrLatency() function in PPCInstrInfo
140 return PPCGenInstrInfo::getInstrLatency(ItinData, MI, PredCost); in getInstrLatency()
192 Latency = getInstrLatency(ItinData, DefMI); in getOperandLatency()
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| /netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/ |
| H A D | ScheduleDAGSDNodes.cpp | 643 SU->Latency += TII->getInstrLatency(InstrItins, N); in computeLatency()
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