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Searched refs:getImm (Results 1 – 25 of 378) sorted by relevance

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/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DR600ClauseMergePass.cpp79 .getImm(); in getCFAluSize()
86 .getImm(); in isCFAluEnabled()
127 if (LatrCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
128 RootCFAlu.getOperand(Mode0Idx).getImm() && in mergeIfPossible()
129 (LatrCFAlu.getOperand(KBank0Idx).getImm() != in mergeIfPossible()
130 RootCFAlu.getOperand(KBank0Idx).getImm() || in mergeIfPossible()
131 LatrCFAlu.getOperand(KBank0LineIdx).getImm() != in mergeIfPossible()
132 RootCFAlu.getOperand(KBank0LineIdx).getImm())) { in mergeIfPossible()
143 if (LatrCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
144 RootCFAlu.getOperand(Mode1Idx).getImm() && in mergeIfPossible()
[all …]
H A DGCNDPPCombine.cpp230 assert(0LL == (Mod0->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))); in createDPPInst()
231 DPPInst.addImm(Mod0->getImm()); in createDPPInst()
253 assert(0LL == (Mod1->getImm() & ~(SISrcMods::ABS | SISrcMods::NEG))); in createDPPInst()
254 DPPInst.addImm(Mod1->getImm()); in createDPPInst()
313 if (OldOpnd->getImm() == 0) in isIdentityValue()
320 if (static_cast<uint32_t>(OldOpnd->getImm()) == in isIdentityValue()
326 if (static_cast<int32_t>(OldOpnd->getImm()) == in isIdentityValue()
332 if (static_cast<int32_t>(OldOpnd->getImm()) == in isIdentityValue()
340 if (OldOpnd->getImm() == 1) in isIdentityValue()
381 return (Imm->getImm() & Mask) == Value; in hasNoImmOrEqual()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/MCTargetDesc/
H A DARMInstPrinter.cpp105 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO3.getImm())); in printInst()
116 assert(ARM_AM::getSORegOffset(MO3.getImm()) == 0); in printInst()
127 O << '\t' << ARM_AM::getShiftOpcStr(ARM_AM::getSORegShOp(MO2.getImm())); in printInst()
136 if (ARM_AM::getSORegShOp(MO2.getImm()) == ARM_AM::rrx) { in printInst()
142 << translateShiftImm(ARM_AM::getSORegOffset(MO2.getImm())) << markup(">"); in printInst()
165 MI->getOperand(3).getImm() == -4) { in printInst()
194 MI->getOperand(4).getImm() == 4) { in printInst()
289 switch (MI->getOperand(0).getImm()) { in printInst()
318 O << markup("<imm:") << '#' << formatImm(Op.getImm()) << markup(">"); in printOperand()
362 int32_t OffImm = (int32_t)MO1.getImm(); in printThumbLdrLabelOperand()
[all …]
H A DARMMCCodeEmitter.cpp234 ARM_AM::AMSubMode Mode = (ARM_AM::AMSubMode)MI.getOperand(OpIdx).getImm(); in getLdStmModeOpValue()
329 return MO.getImm(); in getModImmOpValue()
346 unsigned SoImm = MO.getImm(); in getT2SOImmOpValue()
377 return 64 - MI.getOperand(Op).getImm(); in getNEONVcvtImm32OpValue()
578 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
599 int32_t SImm = MO1.getImm(); in EncodeAddrModeOpValues()
627 if (MO.isImm()) return MO.getImm(); in getBranchTargetOpValue()
665 return encodeThumbBLOffset(MO.getImm()); in getThumbBLTargetOpValue()
678 return encodeThumbBLOffset(MO.getImm()); in getThumbBLXTargetOpValue()
690 return (MO.getImm() >> 1); in getThumbBRTargetOpValue()
[all …]
H A DARMMCTargetDesc.cpp42 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 15) && in getMCRDeprecationInfo()
43 (MI.getOperand(1).isImm() && MI.getOperand(1).getImm() == 0) && in getMCRDeprecationInfo()
46 (MI.getOperand(3).isImm() && MI.getOperand(3).getImm() == 7)) { in getMCRDeprecationInfo()
47 if ((MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 4)) { in getMCRDeprecationInfo()
48 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 5) { in getMCRDeprecationInfo()
55 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10) { in getMCRDeprecationInfo()
62 if (MI.getOperand(4).isImm() && MI.getOperand(4).getImm() == 10 && in getMCRDeprecationInfo()
63 (MI.getOperand(5).isImm() && MI.getOperand(5).getImm() == 5)) { in getMCRDeprecationInfo()
69 ((MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 10) || in getMCRDeprecationInfo()
70 (MI.getOperand(0).isImm() && MI.getOperand(0).getImm() == 11))) { in getMCRDeprecationInfo()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/
H A DSystemZAsmPrinter.cpp37 .addImm(MI->getOperand(1).getImm()); in lowerRILow()
42 .addImm(MI->getOperand(2).getImm()); in lowerRILow()
51 .addImm(MI->getOperand(1).getImm()); in lowerRIHigh()
56 .addImm(MI->getOperand(2).getImm()); in lowerRIHigh()
66 .addImm(MI->getOperand(3).getImm()) in lowerRIEfLow()
67 .addImm(MI->getOperand(4).getImm()) in lowerRIEfLow()
68 .addImm(MI->getOperand(5).getImm()); in lowerRIEfLow()
112 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorLoad()
122 .addImm(MI->getOperand(2).getImm()) in lowerSubvectorStore()
142 .addImm(MI->getOperand(0).getImm()) in emitInstruction()
[all …]
H A DSystemZInstrInfo.cpp98 LowOffsetOp.setImm(LowOffsetOp.getImm() + 8); in splitMove()
107 unsigned HighOpcode = getOpcodeForOffset(NewOpcode, HighOffsetOp.getImm()); in splitMove()
108 unsigned LowOpcode = getOpcodeForOffset(NewOpcode, LowOffsetOp.getImm()); in splitMove()
124 OffsetMO.getImm()); in splitAdjDynAlloc()
144 MI.getOperand(1).setImm(uint32_t(MI.getOperand(1).getImm())); in expandRIPseudo()
180 MI.getOperand(2).getImm()); in expandRXYPseudo()
293 unsigned CCValid = WorkingMI.getOperand(3).getImm(); in commuteInstructionImpl()
294 unsigned CCMask = WorkingMI.getOperand(4).getImm(); in commuteInstructionImpl()
313 MI.getOperand(2).getImm() == 0 && MI.getOperand(3).getReg() == 0) { in isSimpleMove()
336 MI.getOperand(1).getImm() != 0 || !MI.getOperand(3).isFI() || in isStackSlotCopy()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/VE/MCTargetDesc/
H A DVEInstPrinter.cpp68 int32_t TruncatedImm = static_cast<int32_t>(MO.getImm()); in printOperand()
90 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
96 MI->getOperand(OpNum + 1).getImm() == 0 && in printMemASXOperand()
97 MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
99 MI->getOperand(OpNum + 2).getImm() == 0) { in printMemASXOperand()
107 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASXOperand()
112 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASXOperand()
134 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
139 if (MI->getOperand(OpNum).isImm() && MI->getOperand(OpNum).getImm() == 0) { in printMemASOperandASX()
141 MI->getOperand(OpNum + 1).getImm() == 0) { in printMemASOperandASX()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/MCTargetDesc/
H A DAMDGPUInstPrinter.cpp60 O << formatHex(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmOperand()
65 O << formatHex(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmOperand()
73 int64_t Imm = MI->getOperand(OpNo).getImm(); in printU16ImmOperand()
82 O << formatDec(MI->getOperand(OpNo).getImm() & 0xf); in printU4ImmDecOperand()
87 O << formatDec(MI->getOperand(OpNo).getImm() & 0xff); in printU8ImmDecOperand()
92 O << formatDec(MI->getOperand(OpNo).getImm() & 0xffff); in printU16ImmDecOperand()
98 O << formatHex(MI->getOperand(OpNo).getImm() & 0xffffffff); in printU32ImmOperand()
103 if (MI->getOperand(OpNo).getImm()) { in printNamedBit()
125 if (MI->getOperand(OpNo).getImm()) { in printMBUFOffset()
134 uint16_t Imm = MI->getOperand(OpNo).getImm(); in printOffset()
[all …]
H A DR600MCCodeEmitter.cpp107 uint32_t InstWord2 = MI.getOperand(2).getImm(); // Offset in encodeInstruction()
116 int64_t Sampler = MI.getOperand(14).getImm(); in encodeInstruction()
119 MI.getOperand(2).getImm(), in encodeInstruction()
120 MI.getOperand(3).getImm(), in encodeInstruction()
121 MI.getOperand(4).getImm(), in encodeInstruction()
122 MI.getOperand(5).getImm() in encodeInstruction()
125 MI.getOperand(6).getImm() & 0x1F, in encodeInstruction()
126 MI.getOperand(7).getImm() & 0x1F, in encodeInstruction()
127 MI.getOperand(8).getImm() & 0x1F in encodeInstruction()
187 return MO.getImm(); in getMachineOpValue()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/AsmParser/
H A DPPCAsmParser.cpp245 int64_t getImm() const { in getImm() function
316 bool isU1Imm() const { return Kind == Immediate && isUInt<1>(getImm()); } in isU1Imm()
317 bool isU2Imm() const { return Kind == Immediate && isUInt<2>(getImm()); } in isU2Imm()
318 bool isU3Imm() const { return Kind == Immediate && isUInt<3>(getImm()); } in isU3Imm()
319 bool isU4Imm() const { return Kind == Immediate && isUInt<4>(getImm()); } in isU4Imm()
320 bool isU5Imm() const { return Kind == Immediate && isUInt<5>(getImm()); } in isU5Imm()
321 bool isS5Imm() const { return Kind == Immediate && isInt<5>(getImm()); } in isS5Imm()
322 bool isU6Imm() const { return Kind == Immediate && isUInt<6>(getImm()); } in isU6Imm()
324 isUInt<6>(getImm()) && in isU6ImmX2()
325 (getImm() & 1) == 0; } in isU6ImmX2()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/MCTargetDesc/
H A DLanaiMCCodeEmitter.cpp115 return static_cast<unsigned>(MCOp.getImm()); in getMachineOpValue()
138 unsigned AluCode = AluOp.getImm(); in adjustPqBits()
145 ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
153 if (LPAC::modifiesOp(AluCode) && ((Op2.isImm() && Op2.getImm() != 0) || in adjustPqBits()
196 assert((LPAC::getAluOp(AluOp.getImm()) == LPAC::ADD) && in getRiMemoryOpValue()
201 assert(isInt<16>(Op2.getImm()) && in getRiMemoryOpValue()
204 Encoding |= (Op2.getImm() & 0xffff); in getRiMemoryOpValue()
205 if (Op2.getImm() != 0) { in getRiMemoryOpValue()
206 if (LPAC::isPreOp(AluOp.getImm())) in getRiMemoryOpValue()
208 if (LPAC::isPostOp(AluOp.getImm())) in getRiMemoryOpValue()
[all …]
H A DLanaiInstPrinter.cpp49 unsigned AluCode = MI->getOperand(3).getImm(); in usesGivenOffset()
51 (MI->getOperand(2).getImm() == AddOffset || in usesGivenOffset()
52 MI->getOperand(2).getImm() == -AddOffset); in usesGivenOffset()
56 unsigned AluCode = MI->getOperand(3).getImm(); in isPreIncrementForm()
61 unsigned AluCode = MI->getOperand(3).getImm(); in isPostIncrementForm()
66 if (MI->getOperand(2).getImm() < 0) in decIncOperator()
156 OS << formatHex(Op.getImm()); in printOperand()
167 OS << '[' << formatHex(Op.getImm()) << ']'; in printMemImmOperand()
181 OS << formatHex(Op.getImm() << 16); in printHi16ImmOperand()
193 OS << formatHex((Op.getImm() << 16) | 0xffff); in printHi16AndImmOperand()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/PowerPC/MCTargetDesc/
H A DPPCInstPrinter.cpp115 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
116 unsigned char MB = MI->getOperand(3).getImm(); in printInst()
117 unsigned char ME = MI->getOperand(4).getImm(); in printInst()
139 unsigned char SH = MI->getOperand(2).getImm(); in printInst()
140 unsigned char ME = MI->getOperand(3).getImm(); in printInst()
162 unsigned char TH = MI->getOperand(0).getImm(); in printInst()
186 unsigned char L = MI->getOperand(0).getImm(); in printInst()
219 unsigned Code = MI->getOperand(OpNo).getImm(); in printPredicateOperand()
316 unsigned Code = MI->getOperand(OpNo).getImm(); in printATBitsAsHint()
326 unsigned int Value = MI->getOperand(OpNo).getImm(); in printU1ImmOperand()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/MCTargetDesc/
H A DAArch64MCCodeEmitter.cpp208 return static_cast<unsigned>(MO.getImm()); in getMachineOpValue()
219 ImmVal = static_cast<uint32_t>(MO.getImm()); in getLdStUImm12OpValue()
240 return MO.getImm(); in getAdrLabelOpValue()
265 assert(AArch64_AM::getShiftType(MO1.getImm()) == AArch64_AM::LSL && in getAddSubImmOpValue()
267 unsigned ShiftVal = AArch64_AM::getShiftValue(MO1.getImm()); in getAddSubImmOpValue()
271 return MO.getImm() | (ShiftVal == 0 ? 0 : (1 << ShiftVal)); in getAddSubImmOpValue()
302 return MO.getImm(); in getCondBranchTargetOpValue()
324 return MO.getImm(); in getLoadLiteralOpValue()
340 unsigned SignExtend = MI.getOperand(OpIdx).getImm(); in getMemExtendOpValue()
341 unsigned DoShift = MI.getOperand(OpIdx + 1).getImm(); in getMemExtendOpValue()
[all …]
H A DAArch64InstPrinter.cpp82 if (Op2.isImm() && Op2.getImm() == 0 && Op3.isImm()) { in printInst()
85 switch (Op3.getImm()) { in printInst()
121 int64_t immr = Op2.getImm(); in printInst()
122 int64_t imms = Op3.getImm(); in printInst()
152 if (Op2.getImm() > Op3.getImm()) { in printInst()
155 << ", #" << (Is64Bit ? 64 : 32) - Op2.getImm() << ", #" << Op3.getImm() + 1; in printInst()
163 << ", #" << Op2.getImm() << ", #" << Op3.getImm() - Op2.getImm() + 1; in printInst()
171 int ImmR = MI->getOperand(3).getImm(); in printInst()
172 int ImmS = MI->getOperand(4).getImm(); in printInst()
239 int Shift = MI->getOperand(2).getImm(); in printInst()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/AsmParser/
H A DLanaiAsmParser.cpp161 const MCExpr *getImm() const { in getImm() function
409 addExpr(Inst, getImm()); in addImmOperands()
414 addExpr(Inst, getImm()); in addBrTargetOperands()
419 addExpr(Inst, getImm()); in addCallTargetOperands()
424 addExpr(Inst, getImm()); in addCondCodeOperands()
458 addExpr(Inst, getImm()); in addImmShiftOperands()
463 addExpr(Inst, getImm()); in addImm10Operands()
468 if (const MCConstantExpr *ConstExpr = dyn_cast<MCConstantExpr>(getImm())) in addLoImm16Operands()
471 else if (isa<LanaiMCExpr>(getImm())) { in addLoImm16Operands()
473 const LanaiMCExpr *SymbolRefExpr = dyn_cast<LanaiMCExpr>(getImm()); in addLoImm16Operands()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/WebAssembly/MCTargetDesc/
H A DWebAssemblyMCCodeEmitter.cpp100 encodeSLEB128(int32_t(MO.getImm()), OS); in encodeInstruction()
103 encodeULEB128(uint32_t(MO.getImm()), OS); in encodeInstruction()
106 encodeSLEB128(int64_t(MO.getImm()), OS); in encodeInstruction()
110 OS << uint8_t(MO.getImm()); in encodeInstruction()
113 support::endian::write<uint8_t>(OS, MO.getImm(), support::little); in encodeInstruction()
116 support::endian::write<uint16_t>(OS, MO.getImm(), support::little); in encodeInstruction()
119 support::endian::write<uint32_t>(OS, MO.getImm(), support::little); in encodeInstruction()
122 support::endian::write<uint64_t>(OS, MO.getImm(), support::little); in encodeInstruction()
127 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
130 encodeULEB128(uint64_t(MO.getImm()), OS); in encodeInstruction()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID()
51 return MI->getOperand(NBytesPos).getImm(); in getNumPatchBytes()
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID()
105 return getMetaOper(NBytesPos).getImm(); in getNumPatchBytes()
115 return getMetaOper(CCPos).getImm(); in getCallingConv()
122 return MI->getOperand(getMetaIdx(NArgPos)).getImm(); in getNumCallArgs()
189 return MI->getOperand(NumDefs + NCallArgsPos).getImm() + MetaEnd + NumDefs; in getVarIdx()
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID()
208 return MI->getOperand(NumDefs + NBytesPos).getImm(); in getNumPatchBytes()
218 return MI->getOperand(getCCIdx()).getImm(); in getCallingConv()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/
H A DAArch64AsmPrinter.cpp320 uint32_t AccessInfo = MI.getOperand(1).getImm(); in LowerHWASAN_CHECK_MEMACCESS()
632 O << MO.getImm(); in printOperand()
701 if (MO.isImm() && MO.getImm() == 0) { in PrintAsmOperand()
980 int64_t CallTarget = Opers.getCallTarget().getImm(); in LowerPATCHPOINT()
1033 CallTargetMCOp = MCOperand::createImm(CallTarget.getImm()); in LowerSTATEPOINT()
1061 static_cast<FaultMaps::FaultKind>(FaultingMI.getOperand(1).getImm()); in LowerFAULTING_OP()
1063 unsigned Opcode = FaultingMI.getOperand(3).getImm(); in LowerFAULTING_OP()
1162 int64_t Imm = MI->getOperand(0).getImm(); in emitInstruction()
1206 MI->getOperand(1).getImm() == 0) { in emitInstruction()
1210 TmpInst.addOperand(MCOperand::createImm(MI->getOperand(1).getImm())); in emitInstruction()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/
H A DPseudoProbeInserter.cpp120 return std::hash<uint64_t>()(MI->getOperand(0).getImm()) ^ in runOnMachineFunction()
121 std::hash<uint64_t>()(MI->getOperand(1).getImm()); in runOnMachineFunction()
125 return Left->getOperand(0).getImm() == Right->getOperand(0).getImm() && in runOnMachineFunction()
126 Left->getOperand(1).getImm() == Right->getOperand(1).getImm() && in runOnMachineFunction()
127 Left->getOperand(3).getImm() == Right->getOperand(3).getImm() && in runOnMachineFunction()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/SystemZ/MCTargetDesc/
H A DSystemZInstPrinter.cpp52 O << MO.getImm(); in printOperand()
79 int64_t Value = MI->getOperand(OpNum).getImm(); in printUImmOperand()
86 int64_t Value = MI->getOperand(OpNum).getImm(); in printSImmOperand()
161 O.write_hex(MO.getImm()); in printPCRelOperand()
198 MI->getOperand(OpNum + 1).getImm(), 0, O); in printBDAddrOperand()
204 MI->getOperand(OpNum + 1).getImm(), in printBDXAddrOperand()
211 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); in printBDLAddrOperand()
212 uint64_t Length = MI->getOperand(OpNum + 2).getImm(); in printBDLAddrOperand()
224 uint64_t Disp = MI->getOperand(OpNum + 1).getImm(); in printBDRAddrOperand()
238 MI->getOperand(OpNum + 1).getImm(), in printBDVAddrOperand()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Lanai/
H A DLanaiMemAluCombiner.cpp178 return Op1.getImm() == Op2.getImm(); in isSameOperand()
186 (Op.isImm() && Op.getImm() == 0)); in isZeroOperand()
267 InstrBuilder.addImm(AluOffset.getImm()); in insertMergedInstruction()
311 ((Offset.getImm() == 0 && in isSuitableAluInstr()
314 ((IsSpls && isInt<10>(Op2.getImm())) || in isSuitableAluInstr()
315 (!IsSpls && isInt<16>(Op2.getImm())))) || in isSuitableAluInstr()
316 Offset.getImm() == Op2.getImm())) in isSuitableAluInstr()
376 LPAC::AluCode AluOpcode = static_cast<LPAC::AluCode>(AluOperand.getImm()); in combineMemAluInBasicBlock()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonCopyToCombine.cpp159 bool NotExt = Op1.isImm() && isInt<8>(Op1.getImm()); in isCombinableInstType()
178 return !Op.isImm() || !isInt<N>(Op.getImm()); in isGreaterThanNBitTFRI()
663 int64_t V = HiOperand.getImm(); in emitConst64()
664 V = (V << 32) | (0x0ffffffffLL & LoOperand.getImm()); in emitConst64()
681 .addImm(LoOperand.getImm()); in emitCombineII()
686 .addImm(HiOperand.getImm()) in emitCombineII()
697 .addImm(LoOperand.getImm()); in emitCombineII()
702 .addImm(HiOperand.getImm()) in emitCombineII()
712 .addImm(LoOperand.getImm()); in emitCombineII()
717 .addImm(HiOperand.getImm()) in emitCombineII()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/RISCV/MCTargetDesc/
H A DRISCVInstPrinter.cpp97 O << MO.getImm(); in printOperand()
114 uint64_t Target = Address + MO.getImm(); in printBranchOperand()
119 O << MO.getImm(); in printBranchOperand()
126 unsigned Imm = MI->getOperand(OpNo).getImm(); in printCSRSystemRegister()
137 unsigned FenceArg = MI->getOperand(OpNo).getImm(); in printFenceArg()
155 static_cast<RISCVFPRndMode::RoundingMode>(MI->getOperand(OpNo).getImm()); in printFRMArg()
172 unsigned Imm = MI->getOperand(OpNo).getImm(); in printVTypeI()

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