Home
last modified time | relevance | path

Searched refs:getID (Results 1 – 25 of 158) sorted by relevance

1234567

/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/SelectionDAG/
H A DResourcePriorityQueue.cpp64 RegLimit[RC->getID()] = TRI->getRegPressureLimit(RC, *IS->MF); in ResourcePriorityQueue()
99 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValPredInSU()
137 && (TLI->getRegClassFor(VT)->getID() == RCId)) { in numberRCValSuccInSU()
334 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
345 && TLI->getRegClassFor(VT)->getID() == RCId) in rawRegPressureDelta()
365 RegBalance += rawRegPressureDelta(SU, RC->getID()); in regPressureDelta()
369 if ((RegPressure[RC->getID()] + in regPressureDelta()
370 rawRegPressureDelta(SU, RC->getID()) > 0) && in regPressureDelta()
371 (RegPressure[RC->getID()] + in regPressureDelta()
372 rawRegPressureDelta(SU, RC->getID()) >= RegLimit[RC->getID()])) in regPressureDelta()
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/lib/Frontend/
H A DTextDiagnosticPrinter.cpp58 if (Info.getID() == diag::fatal_too_many_errors) { in printDiagnosticOptions()
73 DiagnosticIDs::isBuiltinWarningOrExtension(Info.getID()) && in printDiagnosticOptions()
74 !DiagnosticIDs::isDefaultMappingAsError(Info.getID())) { in printDiagnosticOptions()
79 StringRef Opt = DiagnosticIDs::getWarningOptionForDiag(Info.getID()); in printDiagnosticOptions()
93 DiagnosticIDs::getCategoryNumberForDiag(Info.getID()); in printDiagnosticOptions()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/CodeGen/GlobalISel/
H A DRegisterBank.cpp63 return ContainedRegClasses.test(RC.getID()); in covers()
76 assert((OtherRB.getID() != getID() || &OtherRB == this) && in operator ==()
92 OS << "(ID:" << getID() << ", Size:" << getSize() << ")\n" in print()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/Hexagon/
H A DHexagonMachineScheduler.cpp588 << ((Q.getID() == TopQID) ? "(top|" : "(bot|")); in SchedulingCost()
597 if (Q.getID() == TopQID) { in SchedulingCost()
640 if (Q.getID() == TopQID) { in SchedulingCost()
676 if (IsAvailableAmt && pressureChange(SU, Q.getID() != TopQID) > 0 && in SchedulingCost()
692 if (Q.getID() == TopQID && in SchedulingCost()
696 } else if (Q.getID() == BotQID && in SchedulingCost()
705 if (Q.getID() == TopQID && getWeakLeft(SU, true) == 0) { in SchedulingCost()
714 } else if (Q.getID() == BotQID && getWeakLeft(SU, false) == 0) { in SchedulingCost()
731 if (Q.getID() == TopQID) { in SchedulingCost()
798 if ((Q.getID() == TopQID && (*I)->NodeNum < Candidate.SU->NodeNum) in pickNodeFromQueue()
[all …]
H A DHexagonRegisterInfo.cpp92 switch (RC->getID()) { in getCallerSavedRegs()
357 if (!HST.useHVXOps() || NewRC->getID() != Hexagon::HvxWRRegClass.getID()) in shouldCoalesce()
359 bool SmallSrc = SrcRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
360 bool SmallDst = DstRC->getID() == Hexagon::HvxVRRegClass.getID(); in shouldCoalesce()
428 switch (RC.getID()) { in getHexagonSubRegIndex()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/ARM/
H A DARMInstructionSelector.cpp193 assert((RegBank->getID() == ARM::GPRRegBankID || in guessRegClass()
194 RegBank->getID() == ARM::FPRRegBankID) && in guessRegClass()
197 if (RegBank->getID() == ARM::FPRRegBankID) { in guessRegClass()
243 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectMergeValues()
248 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
253 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectMergeValues()
275 RBI.getRegBank(VReg0, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
280 RBI.getRegBank(VReg1, MRI, TRI)->getID() == ARM::GPRRegBankID && in selectUnmergeValues()
285 RBI.getRegBank(VReg2, MRI, TRI)->getID() == ARM::FPRRegBankID && in selectUnmergeValues()
518 if (RBI.getRegBank(Reg, MRI, TRI)->getID() != ExpectedRegBankID) { in validReg()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AMDGPU/
H A DSIMachineScheduler.cpp519 unsigned PredID = Pred->getID(); in addPred()
523 if (PredID == P->getID()) in addPred()
531 return PredID == S.first->getID(); in addPred()
538 unsigned SuccID = Succ->getID(); in addSucc()
542 if (SuccID == S.first->getID()) { in addSucc()
554 [=](SIScheduleBlock *P) { return SuccID == P->getID(); }) && in addSucc()
630 return CurrentBlocks[Node2CurrentBlock[SU->NodeNum]]->getID() == ID; in isSUInBlock()
1287 if (!--TopDownBlock2Index[Pred->getID()]) in topologicalSort()
1288 WorkList.push_back(Pred->getID()); in topologicalSort()
1297 assert(TopDownBlock2Index[i] > TopDownBlock2Index[Pred->getID()] && in topologicalSort()
[all …]
H A DAMDGPUInstructionSelector.cpp88 return RB->getID() == AMDGPU::VCCRegBankID; in isVCC()
284 if (DstRB->getID() != AMDGPU::SGPRRegBankID && in selectG_AND_OR_XOR()
285 DstRB->getID() != AMDGPU::VCCRegBankID) in selectG_AND_OR_XOR()
288 bool Is64 = Size > 32 || (DstRB->getID() == AMDGPU::VCCRegBankID && in selectG_AND_OR_XOR()
311 const bool IsSALU = DstRB->getID() == AMDGPU::SGPRRegBankID; in selectG_ADD_SUB()
600 if (DstBank->getID() != AMDGPU::SGPRRegBankID) in selectG_BUILD_VECTOR_TRUNC()
1138 const bool IsVALU = DstBank->getID() == AMDGPU::VGPRRegBankID; in selectRelocConstant()
1160 unsigned Mov = DstRB->getID() == AMDGPU::SGPRRegBankID ? in selectGroupStaticSize()
1328 if (OffsetRB->getID() != AMDGPU::SGPRRegBankID) in selectDSGWSIntrinsic()
1851 const bool IsVALU = DstRB->getID() == AMDGPU::VGPRRegBankID; in selectG_TRUNC()
[all …]
/netbsd-src/external/apache2/llvm/dist/clang/tools/libclang/
H A DCXStoredDiagnostic.cpp53 unsigned ID = Diag.getID(); in getDiagnosticOption()
71 return DiagnosticIDs::getCategoryNumberForDiag(Diag.getID()); in getCategory()
75 unsigned catID = DiagnosticIDs::getCategoryNumberForDiag(Diag.getID()); in getCategoryText()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Option/
H A DOptSpecifier.h29 unsigned getID() const { return ID; } in getID() function
31 bool operator==(OptSpecifier Opt) const { return ID == Opt.getID(); }
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/X86/
H A DX86InstructionSelector.cpp171 if (RB.getID() == X86::GPRRegBankID) { in getRegClass()
181 if (RB.getID() == X86::VECRRegBankID) { in getRegClass()
245 if (DstSize > SrcSize && SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
246 DstRegBank.getID() == X86::GPRRegBankID) { in selectCopy()
281 if (SrcRegBank.getID() == X86::GPRRegBankID && in selectCopy()
282 DstRegBank.getID() == X86::GPRRegBankID && SrcSize > DstSize && in selectCopy()
405 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
408 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
411 if (X86::GPRRegBankID == RB.getID()) in getLoadStoreOp()
413 if (X86::VECRRegBankID == RB.getID()) in getLoadStoreOp()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Option/
H A DOption.cpp100 if (getID() == Opt.getID()) in matches()
242 if (getID() == UnaliasedOption.getID()) in accept()
H A DArgList.cpp40 OptRanges.insert(std::make_pair(O.getID(), emptyRange())).first->second; in append()
54 OptRanges.erase(Id.getID()); in eraseArg()
61 auto I = OptRanges.find(Id.getID()); in getRange()
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/Analysis/
H A DMemorySSA.h219 inline unsigned getID() const;
341 OptimizedID = DMA->getID();
346 return getDefiningAccess() && OptimizedID == getDefiningAccess()->getID();
400 OptimizedID = MA->getID();
408 return getOptimized() && OptimizedID == getOptimized()->getID();
418 unsigned getID() const { return ID; }
636 unsigned getID() const { return ID; }
665 inline unsigned MemoryAccess::getID() const {
669 return MD->getID();
670 return cast<MemoryPhi>(this)->getID();
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/
H A DTargetRegisterInfo.h69 unsigned getID() const { return MC->getID(); } in getID() function
125 unsigned ID = RC->getID(); in hasSubClassEq()
720 return RCInfos[getNumRegClasses() * HwMode + RC.getID()]; in getRegClassInfo()
1230 bool isValid() const { return getID() != NumRegClasses; } in isValid()
1233 unsigned getID() const { return ID; } in getID() function
H A DStackMaps.h47 uint64_t getID() const { return MI->getOperand(IDPos).getImm(); } in getID() function
101 uint64_t getID() const { return getMetaOper(IDPos).getImm(); } in getID() function
204 uint64_t getID() const { return MI->getOperand(NumDefs + IDPos).getImm(); } in getID() function
/netbsd-src/external/apache2/llvm/dist/clang/lib/ARCMigrate/
H A DTransProtectedScope.cpp120 if (I->getID() == diag::err_switch_into_protected_scope && in ProtectedScopeFixer()
133 assert(DiagI->getID() == diag::err_switch_into_protected_scope); in handleProtectedScopeError()
159 Pass.TA.clearDiagnostic(Diag.getID(), Diag.getLocation()); in handleProtectedNote()
/netbsd-src/external/apache2/llvm/dist/llvm/lib/Target/AArch64/GISel/
H A DAArch64RegisterBankInfo.cpp237 switch (RC.getID()) { in getRegBankFromRegClass()
390 assert((OpdMapper.getInstrMapping().getID() >= 1 && in applyMappingImpl()
391 OpdMapper.getInstrMapping().getID() <= 4) && in applyMappingImpl()
634 getCopyMapping(DstRB->getID(), SrcRB->getID(), Size), in getInstrMapping()
653 getCopyMapping(DstRB.getID(), SrcRB.getID(), Size), in getInstrMapping()
H A DAArch64InstructionSelector.cpp486 if (RB.getID() == AArch64::GPRRegBankID) { in getRegClassForTypeOnBank()
498 if (RB.getID() == AArch64::FPRRegBankID) { in getRegClassForTypeOnBank()
518 unsigned RegBankID = RB.getID(); in getMinClassForRegBank()
581 switch (RB.getID()) { in getMinSizeForRegBank()
793 assert((DstSize <= 64 || DstBank.getID() == AArch64::FPRRegBankID) && in isValidCopy()
1046 assert(RBI.getRegBank(False, MRI, TRI)->getID() == in emitSelect()
1047 RBI.getRegBank(True, MRI, TRI)->getID() && in emitSelect()
1056 if (RBI.getRegBank(True, MRI, TRI)->getID() != AArch64::GPRRegBankID) { in emitSelect()
1443 assert(RBI.getRegBank(CompareReg, MRI, TRI)->getID() == in emitCBZ()
1924 if (RBI.getRegBank(SrcReg, MRI, TRI)->getID() == AArch64::FPRRegBankID) { in preISelLower()
[all …]
/netbsd-src/external/apache2/llvm/dist/llvm/include/llvm/CodeGen/GlobalISel/
H A DRegisterBankInfo.h231 unsigned getID() const { return ID; } in getID() function
255 return getID() != InvalidMappingID && OperandsMapping; in isValid()
717 if (OpdMapper.getInstrMapping().getID() == DefaultMappingID) in applyMapping()
/netbsd-src/external/apache2/llvm/dist/llvm/utils/TableGen/
H A DDAGISelEmitter.cpp118 return LHS->getID() < RHS->getID(); in operator ()()
H A DGICombinerEmitter.cpp199 RuleID getID() const { return ID; } in getID() function in __anon31f3a7ff0111::CombineRule
331 format("__anon%" PRIu64 "_%u", Rule.getID(), Rule.allocUID()))); in makeNameForAnonInstr()
340 format("__anonpred%" PRIu64 "_%u", Rule.getID(), Rule.allocUID()))); in makeNameForAnonPredicate()
634 SS << "return " << EnumeratedRule.getID() << ";\n"; in emitNameMatcher()
742 << Indent << "if (!RuleConfig->isRuleDisabled(" << Rule->getID() in generateCodeForTree()
/netbsd-src/external/apache2/llvm/dist/clang/lib/Analysis/
H A DProgramPoint.cpp73 Out << RS->getID(Context) << ", \"stmt\": "; in printJson()
191 << "\", \"stmt_id\": " << S->getID(Context) in printJson()
/netbsd-src/external/apache2/llvm/dist/clang/lib/StaticAnalyzer/Core/
H A DExplodedGraph.cpp287 getFirstPred()->getState()->getID() == getState()->getID() && in isTrivial()
498 N->getID(), N->isSink()); in trim()
/netbsd-src/external/apache2/llvm/dist/clang/lib/AST/
H A DCommentLexer.cpp434 T.setCommandID(Info->getID()); in lexCommentText()
473 T.setVerbatimBlockID(Info->getID()); in setupAndLexVerbatimBlock()
512 T.setVerbatimBlockID(Traits.getCommandInfo(Name)->getID()); in lexVerbatimBlockFirstLine()
552 T.setVerbatimLineID(Info->getID()); in setupAndLexVerbatimLine()

1234567